ox16pci958 Oxford Electrical Products, ox16pci958 Datasheet - Page 12

• Manufacturer Part Number: ox16pci958
• Description: Octal Uart With Interface
• Manufacturer: Oxford Electrical Products

OXFORD SEMICONDUCTOR LTD.
Command Register
This register enables certain features of the
PCI interface.
Class-Code Register
This register is read-only via configuration
accesses, and returns the current value of the
PCC register.
Revision ID Register
This register is read-only via configuration
accesses, and returns the current value of the
REV register.
BIST Register
This byte always returns 00h, and writes to the
byte are ignored, as there is no BIST function.
Header Type
This byte always returns 00h, indicating a type
0 header and a single-function device. Writes
to the byte are ignored.
DS-0022 Nov 05
Bits
10
9
8
7
6
5
4
3
2
1
0
Description
1—disables INTA# assertion
0—enables INTA# assertion
After RST# is 0
0
1—enables. the function to report
address parity errors via SERR#
0
1—enables the function to report parity
errors via PERR#
0
0
0
0
Controls the response to memory space
accesses.
1—allows the device respond to the PCI
bus memory accesses as a target
Controls the response to I/O accesses.
1—allows the device respond to the PCI
bus I/O accesses as a target
External—Free Release
Latency Timer
Read-only register always returns 00h. (Not
relevant for target-only PCI devices).
Cache Line Size
This register is read-only and always returns
00h. (The device does not support cache line
wrap mode)
Base Address Register 0
This register sets the PCI base address in
memory
configuration registers. The register has bits
31-7 writable, and the remainder of the bits are
always 0. This forms a request for 128 bytes of
memory space with a 32-bit address, marked
as non-prefetchable. Accesses made to the
memory range defined by this BAR map to
internal configuration registers at internal
addresses 00h-07h.
Base Address Register 1
This register sets the PCI base address in I/O
space for access to local configuration
registers. The register has bits 31:7 writable;
the remainder are always 01h. This forms a
request for 128 bytes of I/O space. Accesses
made to the I/O range defined by this BAR
map to internal configuration registers at
internal addresses 00h-07h.
Base Address Register 2
This base address register is for a mapping of
64 bytes in I/O space. Accesses made to the
I/O range defined by this BAR map to internal
UARTs at internal addresses 80h-BFh.
Base Address Register 3
This base address register is for a mapping of
16 bytes in I/O space. Accesses made to the
I/O range defined by this BAR map to unused
internal addresses C0h-CFh.
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