ox16pci958 Oxford Electrical Products, ox16pci958 Datasheet - Page 19

• Manufacturer Part Number: ox16pci958
• Description: Octal Uart With Interface
• Manufacturer: Oxford Electrical Products

OXFORD SEMICONDUCTOR LTD.
Register
Mnemonic,
Access†
RBR
(read only)
A=0, DLAB=0
THR
(write only)
A=0, DLAB=0
DLL
A=0, DLAB=1
DLM
A=1, DLAB=1
IER
A=1, DLAB=0
FCR
(write only)
A=2
IIR
(read only)
A=2
LCR
A=3
MCR
A=4
LSR
(read only)
A=5
MSR
(read only)
A=6
IRSR
(write only)
A=6
PCR
A=8
SCC
A=9
SCR
A=7, IRSR=0
DS-0022 Nov 05
Register Bit Number
Bit 7
Data Bit 7
(MSB)
Data Bit 7
Bit 7
Bit 15
0
Receiver
Trigger
(MSB)
FIFOs
Enabled
(DLAB)
Divisor
latch
access bit
0
Error in
Receiver
FIFO
(DCD)
Data
carrier
detect
Bit 7
RFU
Indexed
reg safety
catch
Bit 7
‡
‡
Bit 6
Data Bit 6
Data Bit 6
Bit 6
Bit 14
0
Receiver
Trigger
(LSB)
FIFOs
Enabled
Set break
0
Transmitte
r Empty
(TEMT)
(RI)
Ring
indicator
Bit 6
RFU
RFU
Bit 6
Table 15 UART Register Summary
‡
Bit 5
Data Bit 5
Data Bit 5
Bit 5
Bit 13
Low power
enable
(ignored)
0
0
Stick
parity
AFE
Transmit
holding
register
(THRE)
(DSR)
Data set
ready
Bit 5
Clock
select bit 1
RFU
Bit 5
External—Free Release
Bit 4
Data Bit 4
Data Bit 4
Bit 4
Bit 12
Sleep
mode
enable
(ignored)
0
0
(EPS)
Even
parity
select
Loop
Break
Interrupt
(BI)
(CTS)
Clear to
send
Bit 4
Clock
select bit 0
RFU
Bit 4
Bit 3
Data Bit 3
Data Bit 3
Bit 3
Bit 11
(EDSSI)
Enable
modem
status
interrupt
DMA
mode
select
(ignored)
Interrupt
ID Bit 3
(PEN)
Parity
enable
OUT2
(interrupt
enable)
Framing
Error
(FE)
(∆DCD)
Delta data
carrier
detect
Bit 3
Hold CTS
RFU
Bit 3
‡
Bit 2
Data Bit 2
(ERLSI)
Enable
receiver
line status
interrupt
Transmitte
r FIFO
reset
Interrupt
ID Bit 2
(STB)
Number of
stop bits
OUT1
Parity
Error
(PE)
(TERI)
Trailing
edge ring
indicator
RFU
Data Bit 2
Bit 2
Bit 10
Bit 2
RFU
Bit 2
OX16PCI958 DATA SHEET
Bit 1
Data Bit 1
Data Bit 1
Bit 1
Bit 9
(ETHREI)
Enable
transmitter
buffer
empty
interrupt
Receiver
FIFO reset
Interrupt
ID Bit 1
(WLSB1)
Word
length
select bit 1
RTS
Overrun
Error
(OE)
(∆DSR)
Delta data
set ready
Bit 1
RFU
RFU
Bit 1
Bit 0
Data Bit 0
(LSB)
Data Bit 0
Bit 0
Bit 8
(ERBFI)
Enable
received
data
available
interrupt
FIFO
enable
0 if
interrupt
pending
(WLSB0)
Word
length
select bit 0
DTR
Data
Ready
(DR)
(∆CTS)
Delta clear
to send
Bit 0
RFU
RFU
Bit 0
Page 19