ox16pci958 Oxford Electrical Products, ox16pci958 Datasheet - Page 16

• Manufacturer Part Number: ox16pci958
• Description: Octal Uart With Interface
• Manufacturer: Oxford Electrical Products

OXFORD SEMICONDUCTOR LTD.
4. UART
Each UART in the OX16PCI958 is identical.
The depth of the FIFOs is 32 bytes.
Each UART converts between RS232-format
serial data on separate transmit and receive
lines, and byte-wide I/O writes and reads on
the host interface. Malformed incoming serial
data is flagged along with the data in the
receive FIFO. The state of the UART can be
found at any time by reading status registers,
and modem control (handshaking output) lines
can be individually controlled.
Although polled-mode operation is possible,
the UARTs will usually be operated on a host-
interrupt basis. The interrupt system is
designed to allow efficient handling of interrupt
service requests from the UART, for example
by using the prioritised interrupt identification
register, readable FIFO levels, and tuneable
FIFO trigger levels.
The internal transmitter and receiver logic runs
at a programmable synchronisation factor of
4x, 8x, or 16x the serial baud rate. This
internal clock is generated by dividing a
reference clock by an integer divisor from 1 to
(2
255/8.
4.1.
To prepare the UART for communication, it is
necessary to first configure the serial channel
using the control registers LCR, SFR, DLL and
DLM. These set the number of data and stop
bits, the parity setting and the baud rate.
These registers can be changed at any time,
but if data is being received or transmitted
then corruption of the serial data is likely to
occur.
It is also a good idea to enable FIFOs using
FCR and UCR, to decrease the number of
data-transfer services the UART will require.
The trigger levels can also be set at this stage
using RFTR, RITR and TITR, although the
TL16C550-compatible method using FCR7:6
will still work. If appropriate, auto-flow control
may be enabled by writing the MCR, and the
same register sets the initial state of the output
handshaking lines.
Once
interrupts can be enabled by writing IER and
setting MCR3.
The interrupt handler can read the IIR to
determine what type of event needs servicing:
the interrupt types are prioritised so that if
DS-0022 Nov 05
16
– 1) and a fractional divisor from 8/8 to
the
Programming
FUNCTION
serial
channel
is
configured,
External—Free Release
more than one event needs servicing, the
most urgent one is indicated.
A “transmitter FIFO empty” interrupt is cleared
as soon as the IIR is read, so if there is no
data waiting to be transmitted then no further
action is needed. To restart the flow of
transmitted data, the usual practice is for the
user-mode part of the device driver to add the
data to the software transmit queue and then
kick-start transmission by re-writing to the IER
with its current value (with bit 0 set). This will
re-enable
interrupt and the interrupt handler will handle
the transfer of transmit data to the UART,
pushing another block every time the FIFO
becomes empty.
4.2.
The internal registers of the UART are listed in
Table 13, organized by function with both full
name and mnemonic.
UART Data
Receiver buffer
Transmitter holding
UART Control
LSB divisor latch
MSB divisor latch
Interrupt enable
FIFO control
Line control
Modem control
Synchronisation factor
Clock prescaler
UART configuration
Port control
Receive FIFO flow-control trigger
Receive FIFO interrupt trigger
Transmit FIFO interrupt trigger
Register Selection
Indexed register select
Line control (bit 7)
Safety catch control
Table 13 Accessible UART Registers
Accessible Registers
the
“transmitter
OX16PCI958 DATA SHEET
FIFO
Mnem.
DLL
DLM
IER
FCR
LCR
MCR
SFR
CPR
UCR
PCR
RFTR
RITR
TITR
Mnem.
IRSR
LCR
SCC
Mnem.
RBR
THR
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empty”