ox16pci958 Oxford Electrical Products, ox16pci958 Datasheet - Page 24

• Manufacturer Part Number: ox16pci958
• Description: Octal Uart With Interface
• Manufacturer: Oxford Electrical Products

OXFORD SEMICONDUCTOR LTD.
Value
3:0
0110
1100
0100
0010
0000
0001
FIFO Control Register (FCR)
Write only register at the same location as IIR.
It enables and clears the FIFOs, and sets the
trigger level of the receiver FIFO.
Bits
7:6
2
1
0
0
0
1
1
DS-0022 Nov 05
FCR7
Table 24 Receiver FIFO Trigger Level
Description
Trigger level for receiver FIFO interrupt
1—all bytes in transmitter FIFO are cleared
& counter reset to 0. Does not clear the
multiplexer register. Write 1 to clear
1—clears all bytes in the receiver FIFO &
resets counter. Does not clear the
multiplexer register. Write 1 to clear
1—enables transmit & receive FIFOs; also
enables write access to other FCR bits,
otherwise they are not programmed. An
alteration to this bit clears the FIFOs
Interrupt
Receiver line status
Character time-out
Received data
available
THRE
Modem status
None
0
1
0
1
FCR6
UCR1=0
01
04
08
14
Trigger Level
(Bytes)
UCR1=1
01
8
16
28
Priority
Level
1
2
3
4
5
None
Table 23 Interrupt ID Codes in IIR3:0
Not empty
At least
quarter-
full
At least
half-full
At least
seven-
eighths
full
Source
OE, PE, FE, or BI are set in the LSR
During the last four character times, at least one
character has been waiting in the receive FIFO,
and the FIFO has been inactive.
The receive FIFO has reached its trigger level.
THRE is set in the LSR: the UART is ready to be
given more data to transmit.
At least one of the MSR3:0 bits are set, because
CTS#, DSR#, RI#, or DCD# have changed
No interrupt source active
Desc.
External—Free Release
4.4.
When
interrupts are enabled (FCR0=1, IER0=1,
IER2=1), a receiver interrupt occurs as follows:
1. When
2. In addition to when the FIFO trigger level
3. The receiver line status interrupt (IIR = 06)
4. When a character is transferred from the
Operation
programmed trigger level, the received
data available interrupt is issued to the
host. This is cleared when the FIFO drops
below its programmed trigger level.
is reached, and as the interrupt, is cleared
when the FIFO drops below the trigger
level, the IIR receive data available
indication also occurs.
holds a much higher priority than the
received data available (IIR = 04) interrupt.
deserializer to the receiver FIFO, the data
ready bit (LSR0) is set. When the FIFO is
empty, it is cleared.
FIFO Interrupt Mode
the
the
receiver
FIFO
OX16PCI958 DATA SHEET
FIFO
has
Read RBR
Read RBR until
FIFO drops below
the trigger level
Read IIR or write to
THR
Read MSR
Clear Mechanism
Read LSR
-
and
reached
receiver
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