ox16pci958 Oxford Electrical Products, ox16pci958 Datasheet - Page 25

• Manufacturer Part Number: ox16pci958
• Description: Octal Uart With Interface
• Manufacturer: Oxford Electrical Products

OXFORD SEMICONDUCTOR LTD.
When
interrupts are enabled:
When the transmitter FIFO and THRE interrupt
are enabled (FCR0 = 1, IER1 = 1), transmit
interrupts occur as follows:
The behavior of the THRE interrupt is
summarized in Table 25 terms of what events
cause it to become set and cleared.
DS-0022 Nov 05
1. FIFO time-out interrupt occurs when the
2. The FIFO interrupt is cleared when a
3. When the transmit FIFO is empty, it
4. A minimum of two bytes in the transmit
following conditions exist:
time-out interrupt occurs. When the host
reads one character from the receiver
FIFO, this causes the timer to reset. The
non-occurrence of a time-out interrupt,
causes the time-out timer to reset after a
new character is received, or after the
host reads the receiver FIFO.
causes the transmitter holding register
interrupt [IIR3:0 = 2] to occur. When
either the THR is written to, or the IIR is
read, this event causes the interrupt to be
cleared [IIR3:0 = 1].
FIFO are required, at the same instance
since the last time that THRE = 1, or this
causes the transmit FIFO empty indicator
(LSR5 (THRE) = 1) to be delayed one
character time minus the last stop bit
time. The first transmitter interrupt is
instantaneous after changing FCR0 when
it is enabled.
a. A minimum of one character is still
b. More than four continuous character
c. More than four continuous character
the
present in the FIFO.
times have passed (if two stop bits
are programmed, the second one is
included in this time delay) before a
new serial character is received.
times have passed since the reading
of the FIFO was carried out by the
host.
character received to interrupt an
issued delay of 160 ms at 300 baud
with a 12-bit character.
receiver
This
causes
FIFO
and
a
maximum
receiver
External—Free Release
Event
UART reset or IER1
cleared
IER written with bit 1 set
Transmit FIFO becomes
empty
IIR read
THR written
Number of bytes in
transmit FIFO drops from
TITR+1 to TITR
4.5.
If any, or all of the Interrupt enable masks are
cleared (IER0, IER1, IER2, IER3, or all four =
0) data and error conditions are still available
from the UART by using a polling method.
The user application or driver can check
transmitter, and/or receiver FIFO status by
querying the Line Status Register (LSR).
In Polled mode, the FIFOs continue to store
data in the expected fashion with the
exception that trigger level or time-out flags
are not generated.
Receive FIFO Level Register (RFLR)
This read-only register allows a much faster
emptying of the receiver FIFO, by eliminating
the need to perform an LSR read before each
read of the RBR. If RFLR7 is clear, then the
device driver can immediately perform N reads
of the RBR, where N is the value given by
RFLR6:0.
Transmit FIFO Level Register (TFLR)
This
between 0 and 32, relating to the number of
available spaces in the transmit FIFO.
Bits
7
6:0
Table 25 THRE Interrupt Behavior
read-only
Description
Set if any of the entries in the receiver
FIFO has any of its error flags (parity,
framing, or break error) set. Cleared when
the host reads LSR & there are no
subsequent errors in the FIFO.
Returns a value between 0 and 31, relating
to the number of data entries stored in the
receiver FIFO.
FIFO Polled Mode Operation
register
OX16PCI958 DATA SHEET
Effect on THRE
interrupt
Interrupt cannot occur
until IER1 set
Interrupt is set
immediately if transmit
FIFO empty
Interrupt set
Interrupt cleared
Interrupt cleared
Interrupt set
returns
a
Page 25
value