ox16pci958 Oxford Electrical Products, ox16pci958 Datasheet - Page 23

• Manufacturer Part Number: ox16pci958
• Description: Octal Uart With Interface
• Manufacturer: Oxford Electrical Products

OXFORD SEMICONDUCTOR LTD.
Line Status Register (LSR)
Read-only register that indicates the status of
serial data reception.
Bits
7
6
5
4
3
2
1
0
Note: Writes to LSR are ignored, but it is
recommended to avoid them because there
may be unpredictable results on other UARTs.
DS-0022 Nov 05
Description
Set when a character with a parity, framing,
or break error enters the FIFO. Cleared
when LSR is read & no FIFO characters
have an error flag set.
Set when no character is being transmitted,
& no characters queued for transmission in
THR or transmit FIFO
When FIFOs are disabled, set when THR is
empty & the UART is ready for a new
character to be written to it. When FIFOs are
enabled, set when the FIFO is empty
Break interrupt indicator. A break interrupt or
line break occurs when SIN is held low for
longer than the normal transmission time for
the start, data, parity & stop bits configured.
The interrupt, whatever its length, is queued
like a received character whose data bits are
all cleared & a BI flag is attached to it in the
receive FIFO.
1—the next character to be read from the
RBR has its BI flag set
The UART initially attempts to interpret the
interrupt as a received character, so LSR3 is
set because there was no valid stop bit &
LSR2 may be set if parity bits are enabled
Framing error indicator. When a character
without the expected stop bit is received, a
framing error flag is attached to the
character in the receive FIFO.
1—the next character to be read from the
RBR has its FE flag set
When a character is received with a framing
error, the UART assumes that character
synchronization is lost & attempts to
resynchronize by assuming that what was
sampled as the stop bit of a character is
actually the start bit of the next character
Parity error indicator. When a character is
received that does not have the expected
value where the parity bit is expected, a
parity error flag is attached to the character
in the receive FIFO.
1—the next character to be read from the
RBR has its PE flag set
Overrun error indicator. Set when a
character is received & nowhere for it to be
stored, i.e. the receive FIFO is full. The
character & associated error flags are lost.
Cleared when LSR is read
Data ready indicator. Set when a character
can be read from the RBR or receive FIFO
External—Free Release
Interrupt Enable Register (IER)
IER controls independent enable/disable for
UART interrupt sources. A disabled source
does not cause assertion of IREQ# and its
code does not appear on the IIR.
Bit
3
2
1
0
Interrupt Identification Register (IIR)
IIR indicates the interrupt status of the UART
and information about the FIFO status.
To ensure that the most time-critical interrupt
sources are serviced first, IIR returns a code
indicating the highest-priority interrupt sources
that is currently active. The interrupt sources
are prioritized as follows:
The contents of the IIR are indicated in the
table below.
Bits
7:6
3:1
0
(Highest priority) Receiver line status
Receiver character time out
Receiver data ready
Transmitter holding register empty
(Lowest priority) Modem status
Description
1—enables modem status interrupts
1—enables receiver line status interrupts
1—enables transmitter holding register
empty interrupts
1—in FIFO modes, enables received data
available & character time-out interrupts
Description
Set when FCR0 is set, i.e., the UART is in
a FIFO mode
Identifies the highest-priority interrupt
currently active, as indicated in Table 23.
Cleared when any interrupt is active; set
when no interrupt sources are active
OX16PCI958 DATA SHEET
Page 23