ox16pci958 Oxford Electrical Products, ox16pci958 Datasheet - Page 10

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ox16pci958

Manufacturer Part Number
ox16pci958
Description
Octal Uart With Interface
Manufacturer
Oxford Electrical Products
Datasheet

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Power-Management Control Register
Each two-bit group represents a power-
management level range, as shown in Table 7,
defining whether an element is disabled, which
is shown in Table 8.
This register is set to 00h on a PCI reset.
UART Interrupt State
Each bit in this read-only register reports the
interrupt status of the corresponding internal
UART.
UART Enable
Each
corresponding internal UART to be accessed
on the internal bus, by either the PCI interface
or the EEPROM reader.
SISR Enable
Bit 7 must be set to enable access to the
shared interrupt status register (SISR).
This register is set to 80h on a PCI reset.
UART Configuration
Bit 5 must be set to binary 1 to ensure correct
operation of the UART
DS-0022 Nov 05
Field (Bits)
PM_DRIVER
PM_LCLK
PM_OSC
Table 7 Power Management Group
Value
0 0
0 1
1 0
1 1
bit
Table 8 Element Disabling
in
Description
Never disabled
Disabled in D1, D2 & D3
Disabled in D2 and D3
Disabled in D3 only
this
Control Measure
driver_en output deasserted
Local-side clock gated off
Local-side oscillator disabled
register
enables
External—Free Release
the
Global UART Clock Pre-Divider
This register sets a pre-division value for all
the internal UARTs.
Bit 5—One of the clock pre-division factors,
see Table 9
Bit 2—One of the clock pre-division factors,
see Table 9
After a reset, this register is set to F6h, giving
a divide-by-8 clock setting for all UARTs. For
the standard 14.7456 MHz external crystal,
this gives a 1.8432 MHz effective clock to the
UARTs.
For backwards compatibility, write only one of
the four values in Table 9 to bits 5 and 2:
The above register settings are recommended
for backwards compatibility, but Table 10
shows how the actual control logic operates.
Table 9 Clock Pre-Division Values
Table 10 Clock Division Logic
GCS1
1
1
0
0
Value
F6h
F2h
D6h
D2h
OX16PCI958 DATA SHEET
GCS0
1
0
1
0
Divisor
8
4
2
1
Division
8
4
2
1
Page 10

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