ox16pci958 Oxford Electrical Products, ox16pci958 Datasheet - Page 21

• Manufacturer Part Number: ox16pci958
• Description: Octal Uart With Interface
• Manufacturer: Oxford Electrical Products

OXFORD SEMICONDUCTOR LTD.
Master Reset
The UARTs are reset when PCI RESET# is
asserted. Table 16 and Table 17 summarize
the effect of reset on the UART circuits.
UART
Register
LSR
MCR
IER
FCR
IIR
LCR
TFTR
MSR
IRSR
SCR
LSB & MSB
RBR
THR
RFTR
RITR
UCR
WER
Interrupt
Type
modem status
changes
receiver data
ready
RCVR errors
THRE
DS-0022 Nov 05
Table 16 Effect of RESET on UART Signals
UART Signal
DTR#
RTS#
SOUT
Table 17 Effect of RESET on UART
Table 18 Effect of RESET on UART
Register reset state
Bits 6 & 5 set
All bits cleared
Note bits 7:6 permanently cleared
All bits cleared
Note bits 7:6 permanently cleared
All bits cleared
Bits 7,6,3,2,1 cleared
Bit 0 is set
All bits are cleared
Bits 3–0 cleared
Bits 7–4 input signals
All bits cleared
All bits cleared
All bits cleared
All bits cleared
All bits cleared
All bits are cleared
All bits are cleared
All bits are cleared
Bits 7,4,3,2,1,0 cleared
All bits are cleared
All bits cleared
Reset Control
Reset/Read MSR
Reset/Read RBR
Reset/Read LSR
Reset/Read
IIR/Write THR
Reset control
Reset
Reset
Reset
Interrupts
Registers
Signal
Reset State
High
High
High
Low
Low
Low
Interrupt
Reset
State
Low
External—Free Release
FIFO
Receiver
FIFO
Transmitter
FIFO
Serial Data Format
A 0 in RBR or THR corresponds to a logic low
on SIN or SOUT, and a 1 in RBR or THR
corresponds to a logic high on SIN or SOUT.
Bit 0 is always the least significant bit (LSB)
and is the first bit to be serially transmitted or
received.
A start bit or line break state corresponds to a
logic low on SIN or SOUT, and a stop bit or
inter-byte marking state corresponds to a logic
high on SIN or SOUT.
4.3.
The status of the receiver is given by the Line
Status Register (LSR).
The control of the receiver section and format
of the data characters such as number of data
bits, parity, etc is controlled by the Line Control
Register (LCR). Note if parity is used (LCR3)
then the polarity of parity LCR4 is required.
As serial asynchronous data is fed into the
receiver serial data input terminal SIN, the
UART continually looks for a high-to-low
transition. Upon detection of the transition, an
internal counter is reset and counts the
SF clock input to SF/2, which is the centre of
the start bit. (SF is the Synchronisation Factor)
The receiver is prevented from assembling a
false data character caused by noise on the
SIN input, by verification of the start bits. Note:
The start bit is valid only if SIN is still low.
The
Receiver Buffer Register (RBR) which is a
FIFO and a Receiver Deserializer Register
(RDR). Data fed into the receiver serial data
input terminal SIN is deserialized by the RDR
and is fed into RBR.
The control of the receiver section and format
of the data characters such as number of data
bits, parity, etc is controlled by LCR. Note if
parity is used (LCR3) then the polarity of parity
LCR4 is required.
The receiver timing is supplied by the baud
clock generator.
Table 19 Effect of RESET on UART FIFOs
UART
Transmitter/Receiver Section
Reset Control
Reset
FCR1–FCR0
Reset
FCR1–FCR0
FCR0
FCR0
receiver
OX16PCI958 DATA SHEET
section
FIFO Reset State
FIFO empty
FIFO empty
contains
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