ox16pci958 Oxford Electrical Products, ox16pci958 Datasheet - Page 11

• Manufacturer Part Number: ox16pci958
• Description: Octal Uart With Interface
• Manufacturer: Oxford Electrical Products

OXFORD SEMICONDUCTOR LTD.
3.3.
The PCI interface presents a type 0 configuration register set in configuration space, with the
standard extension for power management. Table 11 summarizes the PCI configuration space
registers.
Address
Offset
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
Device ID Register
This register is read-only via configuration
accesses, and returns the current value of the
DID register (see section 3.4 for details of this
and other PCI set-up registers).
Vendor ID Register
This register is read-only via configuration
accesses, and returns the current value of the
VID register.
Status Register
This register records information on the PCI
interface state, as described in the PCI
specification.
Write 1 to bits 11, 14 and 15 to clear them, all
others are read-only.
DS-0022 Nov 05
PCI Configuration Space Registers
Configuration register
31
Device ID
Status
Class code
BIST
Base address register 0 (BAR0)
Base address register 1 (BAR1)
Base address register 2 (BAR2)
Base address register 3 (BAR3)
Base address register 4 (BAR4)
Base address register 5 (BAR5)
Cardbus CIS pointer
Subsystem device ID
Expansion ROM base address register
RFU
RFU
Max_lat
Power management capabilities (PMC)
PM_Data
24
Table 11 PCI Configuration Space Registers
23
Header type
Min_gnt
PMCSR_BSE
External—Free Release
16
Bits
15
14
13
12
11
10:9
8
7
5
4
3
15
Vendor ID
Command
Latency timer
Subsystem vendor ID
Interrupt pin
Next Ptr (always 0)
PMC Control/Status register (PMCSR)
Description
1—parity error, even if parity error
handling is disabled by bit 6 in the
Command register
Set whenever the device asserts SERR#.
0
0
Set whenever the device terminates a
transaction with Target-Abort.
Device select timing. Target access
timing of the function via the DEVSEL#
output. This device is a medium speed
target device (01b)
0
0
0
1
Reflects the interrupt state in the
device/function. INTA# is only asserted
when the Interrupt Disable bit in
Command is 0 & this Interrupt Status bit
is a 1. Setting the Interrupt Disable bit to
a 1 has no effect on the state of this bit.
8
OX16PCI958 DATA SHEET
7
Revision ID
Cache line size
Capabilities pointer
Interrupt line
Cap_ID (always 0)
0
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