ox16pci958 Oxford Electrical Products, ox16pci958 Datasheet - Page 22

• Manufacturer Part Number: ox16pci958
• Description: Octal Uart With Interface
• Manufacturer: Oxford Electrical Products

OXFORD SEMICONDUCTOR LTD.
In FIFO modes, FCR is used to enable and
reset the receiver FIFO and also can be used
to set data trigger levels for when interrupts
are generated.
In non FIFO mode (16C450 style), when the
received data available interrupt is enabled, an
interrupt is generated when a character is
placed in the receiver buffer register. When
RBR is read, the interrupt is cleared.
Transmitter Holding Register & Multiplexer
Register (THR & TMR)
The UART transmitter section contains a
Transmitter Holding Register (THR), which is a
FIFO, and a transmitter multiplexer register
(TMR). THR receives data off the internal data
bus and moves it into the TMR, while the
transmitter is idle, which serializes the data
and outputs it to the transmitter data serial
output terminal SOUT.
The transmitter timing is supplied by the baud
clock generator.
In FIFO modes, FCR is used to enable and
reset the transmitter FIFOs and can be used to
set data trigger levels for when interrupts are
generated. For more details see Section 4.2.
In non FIFO mode (16C450), when the
transmitter holding register empty interrupt is
enabled, an interrupt is generated when THR
is empty. When a character is loaded into the
register, the interrupt is cleared.
Line Control Register (LCR)
LCR controls the format of the data character
and is applicable to both transmitter and
receiver.
contents are described below.
Bits
7
6
5
4
DS-0022 Nov 05
Description
Divisor latch access bit (DLAB)
1—enables access to DLL & DLM
0—enables access to IER, THR &RBR
1—SOUT is forced to the spacing state (low)
1—If LCR3 is 1, parity bit transmission &
reception is the state opposite to LCR4
value. If LCR4 is 1, even parity enabled. (or
cleared parity enabled, if LCR5 is 1)
0—odd parity enabled (or set parity enabled,
if LCR5 is 1)
This forces parity to a known state
1—even parity enabled. (or cleared parity is
enabled, if LCR5 is 1)
0—odd parity enabled (or set parity enabled,
if LCR5 is 1).
The
LCR
is
read-writable.
External—Free Release
Its
Bits
3
2
1:0
Use the following steps to create a line break:
Note: no invalid characters are transmitted
because of the break.
1. When THRE empty status occurs, load a
2. After the next THRE, set the break
3. When TEMT is set to high, wait for the
4. Clear the break when the transmission
Table 22 Stop Bit Length Selection
zero byte
transmitter to be idle
has to be re-established.
Table 21 Word Length Selection
Description
1—a parity bit is generated between the last
data word bit & stop bit in data transmitted &
checked by the receiver
0—no parity is selected; see Table 20
Specifies either one or two stop bits in each
transmitted character.
0—one stop bit is generated in the data
1—1½ or 2 stop bits are generated in the
data: see Table 22. The receiver clocks only
the first stop bit, regardless of the number of
stop bits selected
These two bits specify the number of bits in
each transmitted or received serial
character; see Table 21
LCR2:0
0 X X
1 0 0
1 0 1
1 1 0
1 1 1
LCR1:0
0 0
0 1
1 0
1 1
LCR5:3
X X 0
0 0 1
0 1 1
1 0 1
1 1 1
Table 20 Parity Selection
Description
1 stop bit generated
1½ stop bits generated
2 stop bits generated
2 stop bits generated
2 stop bits generated
OX16PCI958 DATA SHEET
Description
No parity
Odd parity
Even parity
Set parity
Cleared parity
Description
Word length is 5 bits
Word length is 6 bits
Word length is 7 bits
Word length is 8 bits
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