tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 79

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
register bit is set and when the bus is released.
When P50–P57 are configured as analog channels of the ADC, the ADCH[2:0] field in A/D Mode Control
Register 1 (ADMOD1) is used to select a channel(s). See Section 15.1.
When P53 is configured as ADTRG , the ADTRGE bit in the ADMOD1 register is used to enable and disable
the external trigger input to the ADC.
When INT0–INT4 are enabled for a wake-up from STOP mode with the SYSCR2.DRIVE bit cleared (undriven
pins), the corresponding bit in the PnFC must be set.
When P96–P97 are configured as output ports, they function as open-drain outputs.
When P96–P97 are configured as XT1–XT2, the SYSCR0 register must be programmed to enable oscillation,
etc.
When PA6 and PA7 are configured as SDA and SCL outputs for the SBI, the ODEA[7:6] field in the Open-Drain
Enable (ODE) register can be used to configure them as either push-pull or open-drain ouptuts. Upon reset,
the default is push-pull. See Section 7.11.
HWR
,
R
/
W
and
P40 to P43 have their internal pullup resistors enabled when the corresponding P4FC
TMP1941AF-39
TMP1941AF
2003-03-27