tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 106

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

8.
External Bus Interface
internal busses and the memory or peripherals in the external address space. It consists of the External Bus
Interface (EBIF) logic and the Chip Select/Wait Controller.
select function supports automatic wait-state generation and data bus sizing (8-bit or 16-bit) for each of the four
address blocks and the rest of the external address locations.
EBIF logic also performs dynamic bus sizing and bus arbitration.
(1) Wait-state generation
(2) Data bus width
(3) Read recovery cycles
(4) ALE pulse width
(5) Bus arbitration
The TMP1941AF contains external bus interface logic that handles the transfer of information between the
The CS/Wait Controller provides four programmable chip select signals, with variable block sizes. The chip
The EBIF logic controls the timing of the external bus, based on the settings of the CS/Wait Controller. The
•
•
cycles inserted between two consecutive external bus cycles.
•
•
Selectable ALE pulse width (0.5 or 1.5 cycles). This setting applies to all the address blocks.
Individually programmable for each address block
Individually programmable (8-bit or 16-bit) for each address block
Individually programmable (to up to 2 cycles) for each address block. Read recovery cycles are dummy
Automatic insertion of up to seven wait cycles
When AM0 = 0
The TMP1941AF has either a mixed 8/16-bit data bus or the 16-bit data bus. The program memory
accessed after reset must be connected with the TMP1941AF with a 16-bit data bus.
When AM1 = 1
The TMP1941AF has a 8-bit data bus. When AM1 is at logic 1, the data bus width settings in the Chip
Select/Wait Control registers are ignored.
WAIT pin
TMP1941AF-66
TMP1941AF
2003-03-27