tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 183

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

TB2MOD
(0xFFFF_F1A2)
Name
Read/Write
Reset Value
Function
Must be written as 00.

7
0
R/W
Figure 12.9 TMRB2 Mode Register

6
0
TMRB2 Mode Register
TMP1941AF-143
Software
capture
0: Capture
1: Don’t
TB2CP0
care
Up-counter (UC2) clear control
Capture triggers
Software capture
W*
5
1
00
01
10
11
0
1
0
1
Capture triggers
00: Disabled
01: TB2IN0↑TB2IN1↑
10: TB2IN0↑TB2IN0↓
11: TA1OUT↑TA1OUT↓
Disabled
UC2is reset upon a match with TB2RG1.
Capture disabled
Latches UC2 value into TB2CP0 at rising edges of TB2IN0.
Latches UC2 value into TB2CP1 at rising edges of TB2IN1.
Latches UC2 value into TB2CP0 at rising edges of TB2IN0.
Latches UC2 value into TB2CP1 at falling edges of TB2IN0.
Latches UC2 value into TB2CP0 at rising edges of TA1OUT.
Latches UC2 value into TB2CP1 at falling edges of TA1OUT.
Latches UC2 value into TB2CP0.
Don’t care
TB2CPM1 TB2CPM0
4
0
3
0
Capture Triggers
UC2 clear
control
0: Disable
1: Enable
TB2CLE
R/W
2
0
TMP1941AF
TMRB2 clock source
00: TB2IN0 input
01: φT1
10: φT4
11: φT16
TB2CLK1
1
0
2003-03-27
TB2CLK0
0
0