tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 337

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

16-Bit Timer Control (1 of 2)
Mnemonic Name Address
19.7 16-Bit Timer/Event Counters (TMRBs)
TB0MOD
TB1MOD
TB2MOD
TB3MOD
TB0RUN
TB1RUN
TB2RUN
TB3RUN
Register
Register
Register
Register
Register
Register
Register
Register
TMRB0
TMRB1
TMRB2
TMRB3
TMRB0
TMRB1
TMRB2
TMRB3
Mode
Mode
Mode
Mode
Run
Run
Run
Run
F1A0H
F1B0H
F1A2H
F1B2H
F180H
F190H
F182H
F192H
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
Double
Buffering
0: Disable
1: Enable
Double
Buffering
0: Disable
1: Enable
Double
Buffering
0: Disable
1: Enable
Double
Buffering
0: Disable
1: Enable
Must be written as 00.
Must be written as 00.
Must be written as 00.
Must be written as 00.
TB0RDE
TB1RDE
TB2RDE
TB3RDE




7
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Must be
written as
0.
Must be
written as
0.
Must be
written as
0.
Must be
written as
0.








TMP1941AF-297
6
0
0
0
0
0
0
0
0
Software
capture
0: Capture
1: Don’t
Software
capture
0: Capture
1: Don’t
Software
capture
0: Capture
1: Don’t
Software
capture
0: Capture
1: Don’t
TB0CP0
TB1CP0
TB2CP0
TB3CP0
care
care
care
care
W*
W*
W*
W*












5
1
1
1
1
Capture triggers
00: Disabled
01: TB0IN0↑TB0IN1↑
10: TB0IN0↑TB0IN0↓
11: TA1OUT↑TA1OUT↓
Capture triggers
00: Disabled
01: TB1IN0↑TB1IN1↑
10: TB1IN0↑TB1IN0↓
11: TA1OUT↑TA1OUT↓
Capture triggers
00: Disabled
01: TB2IN0↑TB2IN1↑
10: TB2IN0↑TB2IN0↓
11: TA1OUT↑TA1OUT↓
Capture triggers
00: Disabled
01: Disabled
10: Disabled
11: TA1OUT↑TA1OUT↓
TB0CPM1
TB1CPM1
TB2CPM1
TB3CPM1












4
0
0
0
0
IDLE
0: Off
1: On
IDLE
0: Off
1: On
IDLE
0: Off
1: On
IDLE
0: Off
1: On
TB0CPM0
TB1CPM0
TB2CPM0
TB3CPM0
I2TB0
I2TB1
I2TB2
I2TB3
3
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
Prescalar
Run/Stop
Control
0: Stop
1: Run
Prescalar
Run/Stop
Control
0: Stop
1: Run
Prescalar
Run/Stop
Control
0: Stop
1: Run
Prescalar
Run/Stop
Control
0: Stop
1: Run
UC0 clear
control
0: Disable
1: Enable
UC1 clear
control
0: Disable
1: Enable
UC2 clear
control
0: Disable
1: Enable
UC3 clear
control
0: Disable
1: Enable
TB0PRUN
TB1PRUN
TB2PRUN
TB3PRUN
TB0CLE
TB1CLE
TB2CLE
TB3CLE
R/W
R/W
R/W
R/W
2
TMP1941AF
0
0
0
0
0
0
0
0
TMRB0 clock source
00: TB0IN0 input
01: φT1
10: φT4
11: φT16
TMRB1 clock source
00: TB1IN0 input
01: φT1
10: φT4
11: φT16
TMRB2 clock source
00: TB2IN0 input
01: φT1
10: φT4
11: φT16
TMRB3 clock source
00: TB3IN0 input
01: φT1
10: φT4
11: φT16
TB0CLK1
TB1CLK1
TB2CLK1
TB3CLK1












1
0
0
0
0
2003-03-27
Run/Stop
Control
0: Stop &
clear
1: Run
Run/Stop
Control
0: Stop &
clear
1: Run
Run/Stop
Control
0: Stop &
clear
1: Run
Run/Stop
Control
0: Stop &
clear
1: Run
TB0CLK0
TB1CLK0
TB2CLK0
TB3CLK0
TB0RUN
TB1RUN
TB2RUN
TB3RUN
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0