tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 152

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Note 1: The prescaler's output clock φ φ φ φ Tn must be selected so that φ φ φ φ Tn < fsys/2 is satisfied.
Note 2: Do not change the clock gear value while the timer is running.
Note 3: The — character means “Don’t use.”
Clock Select
11.2 Timer Components
Peripheral
SYSCR1.
0 (fgear)
FPSEL
11.2.1
1 (fc)
Prescaler
prescalar clock source (φT0) can be selected from fperiph, fperiph/2 and fperiph/4 by programming the
PRCK[1:0] field of the SYSCR0 located within the CG. fperiph can be selected from fgear (geared
clock) and fc (non-geared clock) by programming the FPSEL bit of the SYSCR1 located within the CG.
the TMRA01. A write of 1 to this bit starts the prescalar. A write of 0 to this bit clears and halts the
prescalar.
by-512 (φT256). Table 11.2 shows prescalar output clock resolutions (@fc = 32 MHz).
The TMRA01 has a 9-bit prescalar that slows the rate of a clocking source to the counters. The
The TA01PRUN bit in the TA01RUN register allows the enabling and disabling of the prescalar for
Prescalar output taps can be divide-by-2 (φΤ1), divide-by-8 (φT4), divide-by-32 (φT16) and divide-
Clock Gear
GEAR[1:0]
SYSCR1.
01 (fc/2)
10 (fc/4)
11 (fc/8)
01 (fc/2)
10 (fc/4)
11 (fc/8)
00 (fc)
00 (fc)
Value
Table 11.2 Prescalar Output Clock Resolutions
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
Clock Source
PRCK[1:0]
Prescaler
SYSCR0.
TMP1941AF-112
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
3
2
4
3
5
4
6
5
3
2
3
φT1
(0.2 µs)
(0.1 µs)

(0.4 µs)
(0.2 µs)

(0.8 µs)
(0.4 µs)

(1.6 µs)
(0.8 µs)

(0.2 µs)
(0.1 µs)

(0.2 µs)








Prescalar Output Clock Resolution
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
5
4
3
6
5
4
7
6
5
8
7
6
5
4
3
5
4
3
5
4
5
φT4
(0.8 µs)
(0.4 µs)
(0.2 µs)
(1.6 µs)
(0.8 µs)
(0.4 µs)
(3.2 µs)
(1.6 µs)
(0.8 µs)
(6.4 µs)
(3.2 µs)
(1.6 µs)
(0.8 µs)
(0.4 µs)
(0.2 µs)
(0.8 µs)
(0.4 µs)
(0.2 µs)
(0.8 µs)
(0.4 µs)

(0.8 µs)


fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
10
9
9
7
6
5
8
7
6
8
7
8
7
6
5
7
6
5
7
6
5
7
6
5
φT16
TMP1941AF
(12.8 µs)
(12.8 µs)
(3.2 µs)
(1.6 µs)
(0.8 µs)
(6.4 µs)
(3.2 µs)
(1.6 µs)
(6.4 µs)
(3.2 µs)
(25.6 µs)
(6.4 µs)
(3.2 µs)
(1.6 µs)
(0.8 µs)
(3.2 µs)
(1.6 µs)
(0.8 µs)
(3.2 µs)
(1.6 µs)
(0.8 µs)
(3.2 µs)
(1.6 µs)
(0.8 µs)
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
2003-03-27
@fc = 40 MHz
12
13
12
14
13
12
11
10
11
10
11
11
10
11
10
11
10
11
10
φT256
9
9
9
9
9
(12.8 µs)
(102.4 µs)
(204.8 µs)
(102.4 µs)
(409.6 µs)
(204.8 µs)
(102.4 µs)
(12.8 µs)
(12.8 µs)
(12.8 µs)
(12.8 µs)
(51.2 µs)
(25.6 µs)
(51.2 µs)
(25.6 µs)
(51.2 µs)
(51.2 µs)
(25.6 µs)
(51.2 µs)
(25.6 µs)
(51.2 µs)
(25.6 µs)
(51.2 µs)
(25.6 µs)