tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 231

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Protocol
(1) Put all the master and slave controllers in 9-bit UART mode.
(2) Enables the receiver in each slave controller by setting the SC0MOD0.WU bit to 1.
(3) The master controller transmits an address character (i.e, select code) that identifies a slave
(4) Each slave controller compares the received address to its station address and clears the WU bit if
(5) The master controller transmits data characters or block of data to the selected slave controller
(6) Slave controllers not addressed continue to monitor the data stream, but discard any characters
Note:
TXD
controller. The address character has the most-significant bit (bit 8) set to 1.
they match.
(with SC0MOD0.WU bit cleared). Data characters have the most-significant bit (bit 8) cleared to
0.
with the most-significant bit (RB8) cleared, and thus does not generate receive-done interrupts
(INTRX0). The addressed slave controller with its WU bit cleared can transmit data to the master
controller to notify that it has successfully received the message.
Master
The slave controller’s TXD pin must be configured as an open-drain output by programming the
ODE register.
Figure 13.35 Serial Link Using the Wake-Up Function
RXD
start
start
TXD
bit 0
bit 0
TMP1941AF-191
Slave 1
1
1
Slave controller select code
RXD
2
2
3
3
Data
TXD
4
4
Slave 2
5
5
6
6
RXD
7
7
TMP1941AF
bit 8
“0”
“1”
8
TXD
stop
stop
Slave 3
2003-03-27
RXD