tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 112

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

8.2.4
AD[15:0]
ALE
AD[15:0]
ALE
RD
•
•
•
A[23:16]
AD[15:0]
ALE
Read Recovery Time
next external bus cycle. To allow for a read recovery time, one or two dummy cycles can be inserted
between back-to-back bus cycles. (Dummy cycles can only be inserted immediately after a read.)
from the data bus before the next transfer begins. This provides a sufficient time after the RD strobe
for the previous read is deasserted until the address for the next read or write is placed on the address
bus. Figure 8.10 shows bus cycle timing with one and two dummy cycles inserted into bus cycles.
RD
Following an external bus read cycle, a certain recovery time may be required before initiating the
Dummy cycle insertion is programmable in the CS/Wait Controller.
Dummy cycles insert idle cycles between transfers to enable slow off-chip peripherals to remove data
Between an external read and an external read:
Between an external read and an external write:
After an external write:
Figure 8.10 Read Cycle Timing (with Dummy Cycles Inserted)
1 Dummy Cycle
Read Data
Read Data
Dummy
tsys
DATA
tsys
Figure 8.9 Read Recovery Time
TMP1941AF-72
ADR
Two Dummy Cycles
Upper Address
Next ADR
2 Dummy Cycles
Dummy
DATA
Programmable
Programmable
No dummy cycle
TMP1941AF
ADR
Next ADR
2003-03-27