tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 69

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

6.
6.1
Interrupt Request
Core Processor
Interrupt Request
Nonmaskable
Interrupts
TX19L
Overview
the Clock Generator (CG). The Status register contains the Interrupt Mask Level field (CMask[15:13]) and
the Interrupt Enable bit (IEc). For interrupt processing, also refer to the 32-Bit TX System RISC TX19 Core
Architecture manual.
programmed for active polarity and either level or edge sensitivity. The TMP1941AF interrupts are broadly
grouped as follows:
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Interrupt processing is coordinated bewtween the CP0 Status register, the Interrupt Controller (INTC) and
The TMP1941AF interrupt mechanism includes the following features:
The Interrupt Detection block monitors interrupt events. Each interrupt source can be individually
Note 1: There are interrupt enable and polarity bits in these registers:
Note 2: The TMP1941AF provides six interrupt sources, INT0–INT4 and INTRTC, that can be used for
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External interrupts INT0–INT4 and INTRTC
4 CPU internal interrupts (software interrupts)
12 external interrupt pins ( NMI , INT0 through INTA)
32 on-chip peripheral interrupts
Vector generation for each interrupt source
Programmable priority for each interrupt source (7 levels)
DMA trigger on interrupt
When enabled for STOP/SLEEP wake-up signaling
external interrupts INT0–INT4 or INTRTC is asserted. The EMCGxx field in the IMCGxx register
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STOP/SLEEP wake-up signaling. External interrupts INT5–INTA cannot function as wake-up signals.
The TMP1941AF awakens from STOP or SLEEP mode, if so programmed, when any of the
Interrupt Mode Control registers (IMCxx) in the INTC
IMCGxx registers in the CG
3
Interrupt Clear Register
Figure 6.1 General Interrupt Mechanism
Interrupt Detection
Interrupt Priority
Priority Resolver
Interrupt Vector
Generation
Settings
Block
INTC
TMP1941AF-29
INT0–INT4 bypass the CG unless used for
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STOP/SLEEP wake-up signaling
NMI, INTWDT
Internal interrupt signals
(DMAC, Timers, SIO, SBI, ADC)
INT5–INTA
Interrupt Clear
Detection
Interrupt
Register
Block
CG
5
TMP1941AF
2003-03-27
INT0–INT4
INTRTC
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