tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 227

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Receive Data
Read Timing
SCLK0 Output
RXD0
INTTX0 Interrupt
Receive Data
Read Timing
SCLK0 Input
(SCLKS = 0: Rising Edge)
SCLK0 Input
(SCLKS = 1: Falling Edge)
RXD0
INTRX0 Interrupt
(2) Receive Operations
Note:
synchronization clock is driven out from the SCLK0 pin to shift the next character into Receive
Buffer 1. When a whole 8-bit character has been loaded into Receive Buffer 1, it is transferred to
Receive Buffer 2, and the receive-done interrupt (INTRX0) is generated.
SCLK0 input is activated to shift the next character into Receive Buffer 1. When a whole 8-bit
character has been loaded into Receive Buffer 1, it is transferred to Receive Buffer 2, and the
receive-done interrupt (INTRX0) is generated.
receiver is not ready to accept the next character. In case the CPU reads the character in Receiver
Buffer 2 after point A, reception of the next character begins at that point, causing the received
data to be corrupted. For system applications in which the CPU might not be able to keep pace
with incoming data streams, handshaking is required.
In SCLK Output mode, each time the CPU picks up the character in Receive Buffer 2, the
The SCLK output is initiated by setting the SC0MOD0.RXE bit to 1.
In SCLK Input mode, the CPU must pick up the character in the Receive Buffer 2 before the
The CPU must read the character in Receive Buffer 2 by point A. Until that is done, the
Regardless of whether SCLK is in input mode or output mode, the receiver must be enabled by
setting the SC0MOD.RXE bit to 1 in order to perform receive operations.
Figure 13.31 Receive Operation in I/O Interface Mode (SCLK0 Output Mode)
Figure 13.32 Receive Operation in I/O Interface Mode (SCLK0 Input Mode)
bit 0
bit 0
TMP1941AF-187
bit 1
bit 1
bit 5
bit 6
bit 6
TMP1941AF
bit 7
bit 7
A
2003-03-27
bit 0
bit 0