tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 107

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

8.1
Note 1:
Note 2:
Note 3:
8.1.1
8.1.2
Pin
Functions
Address Lines
Data Lines
Multiplexed
Address/Data Lines
Timing Diagram
Address and Data Buses
Because the data bus is multiplxed with the address bus, even in the C and D configurations, address bits
also appear on the AD bus prior to the data being accepted or provided.
Upon reset, all of Ports 0–2 are configured as general-purpose input ports; programming is required to use
them as address or data bus pins.
Address and data bus configurations are selectable through the programming of the P1CR, P1FC, P2CR
and P2FC registers.
Supported Configurations
A23/A0–A7) pins can be configured as the address and data buses. The TMP1941AF supports the
following four bus configurations.
When AM1 = 0 and AM0 = 0, the address and data buses are configured as shown in (2) below.
States of the Address Bus During On-Chip Address Accesses
presented. During this time, the address/data bus assumes the high-impedance state.
For external memory interface, Port 0 (AD0–AD7), Port 1 (AD8–AD15/A8–A15) and Port 2 (A16–
When AM1 = 0 and AM0 = 1, the address and data buses are configured as shown in (1) below.
While an on-chip address is being accessed, the address bus maintains the previous address externally
Port 0
Port 1
Port 2
A23-8
AD7-0
ALE
RD
24 Max (16 Mbytes)
A7-0
A23-8
AD0–AD7
A16–A23
A8–A15
(1)
8
8
TMP1941AF-67
D7-0
A23-16
AD15-0
ALE
RD
24 Max (16 Mbytes)
A15-0
AD8–AD15
AD0–AD7
A16–A23
A23-8
(2)
16
16
TMP1941AF
D15-0
2003-03-27