tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 52

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

5.1
5.1.1
5.1.2
Clock Generation
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Main System Clock
Subsystem Clock
A crystal can be connected between X1 and X2, or X1 can be externally driven with a clock.
The on-chip PLL can be enabled or disabled (bypassed) during reset by using the PLLOFF pin.
When the PLL is enabled, the input clock frequency is multiplied by four.
The clock gear can be programmed to divide the clock by 2, 4 or 8. (The default is 1/8 on reset.)
Input clock frequency
A 32.768-kHz crystal is connected between XT1 and XT2 (or XT1 can be externally driven with a
clock.)
SLOW mode: The CPU operates off of the low-speed clock.
SLEEP mode: Only the Real-Time Counter (RTC) is operational.
Note 1: The DFOSC bit in the SYSCR1 must be cleared to 0. The default is 0 on reset.
PLL
(For both crystal and external clock)
PLL OFF
Crystal
External clock
TMP1941AF-12
ON
Input Frequency Range
16–20 MHz
16–20 MHz
20–40 MHz
4–10 MHz
20 MHz
40 MHz
20 MHz
20 MHz
fmax
TMP1941AF
1
1.25 MHz
2 MHz
1 MHz
1 MHz
fmin
2003-03-27