tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 153

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

11.2.2
11.2.3
Note:
Up-Counters (UC0 and UC1)
independently selected by the TA01MOD register.
clock applied to the TA0IN pin. Which clock is to use is programmed into the TA0CLK[1:0] field of the
TA01MOD register.
mode, the clock input to the UC1 is always the UC0 overflow output. In other operating modes, the
clock input to the UC1 is either one of three prescalar outputs (φΤ1,φT16, φT256) or the TMRA0
comparator match-detect output.
clear the counter. Upon reset, the up-counter is set to 00H and the whole timer module is disabled.
Timer Registers (TA0REG and TA1REG)
time constant value in the timer register, the comparator block generates a match-detect signal. When
the time constant is set to 00H, a match occurs upon a counter overflow.
enabled and disabled through the programming of the TA0RDE bit in the TA01RUN: 0=disable,
1=enable.
buffer. This takes place upon detection of a 2
UC0 and the TA1REG in PPG mode. Double-buffering must be disabled in interval timer modes.
function, the TA01RUN.TA0RDE bit must be set to1 after loading the TA0REG with a time constant.
When TA01RUN.TA0RDE=1, the next time constant can be written to the register buffer.
The timer module contains two 8-bit binary up-counters, each of which is driven by a clock
The clock input to the UC0 is either one of three prescalar outputs (φΤ1,φT4, φT16) or the external
Possible clock sources for the UC1 depend on the selected operating mode. In 16-bit interval timer
The TA0RUN and TA1RUN bits in the TA01RUN register are used to start counting and to stop and
Each timer register is an 8-bit register containing a time constant. When the up-counter reaches the
One of the two timer registers, TA0REG, is double-buffered. The double-buffering function can be
If double-buffering is enabled, the TA0REG latches a new time constant value from the register
A reset clears the TA01RUN.TA0RDE bit to 0, disabling the double-buffering function. To use this
Figure 11.13 illustrates the double-buffer structure for the TA0REG.
The timer register and the corresponding register buffer are mapped to the same address. When
TA01RUN.TA0RDE=0, a time constant value is written to both of the timer register and the register
buffer; when TA01RUN.TA0RDE=1, a time constant value is written only to the register buffer.
Timer Register 0 (TA0REG)
Comparator (CP0)
Internal Data Bus
Register Buffer 0
Up-Counter
Figure 11.3 Timer Register 0 (TA0REG) Structure
Shift Trigger
Write
TMP1941AF-113
Y
n
TA01RUN.TA0RDE
–1 overflow in PWM mode and upon a match between the
Selector
S
A
B
TA1REG Match in PPG Mode
2
Write to TA0REG
n
-1 Overflow in PWM Mode
TMP1941AF
2003-03-27