tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 263

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

ADMOD1
(0xFFFF_F311)
Name
Read/Write
Reset Value
Function
Note 1: Set the VREFON bit to 1 before setting the ADS bit in the ADMOD0 to start a conversion.
Note 2: The AN3 pin is shared with the ADTRG pin. Therefore, when the external conversion trigger
input ( ADTRG ) is enabled (i.e., when ADMOD1.ADTRGE = 1), the ADCH[2:0] field must not be
programmed to 011.
Figure 15.3 A/D Mode Control Register (ADMOD1)
VREF
control
0: Off
1: On
VREFON
R/W
7
0
ADC
operation
in IDLE
mode
0: Off
1: On
A/D Mode Control Register 1
I2AD
R/W
6
0
TMP1941AF-223



5
Analog Input Channel Select
000
001
010
011 (Note) AN3
100
101
110
111
ADCH[2:0]



4
AN0
AN1
AN2
AN4
AN5
AN6
AN7
A/D external conversion trigger ( ADTRG input)
External
conversion
trigger
0: Disable
1: Enable
Fixed-Channel Mode
ADTRGE
0
1
3
0
Disable
Enable
0
Analog input channel select
ADCH2
2
0
TMP1941AF
SCAN
R/W
AN0
AN0→AN1
AN0→AN1→AN2
AN0→AN1→AN2→AN3
AN4
AN4→AN5
AN4→AN5→AN6
AN4→AN5→AN6→AN7
Channel Scan Mode
ADCH1
1
0
2003-03-27
1
ADCH0
0
0