tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 289

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

18.6 SIO Timing
SCK Output Mode /
Active-High SCL
Active-Low SCK
18.6.1
Input Mode
Input Mode
SCLK
Transmit Data
SCLK
Receive Data
I/O Interface Mode
programming of the clock gear function.
(1) SCLK Input Mode
(2) SCLK Output Mode
(RxD)
* SCLK rise or fall: Measured relative to the programmed active edge of SCLK.
(TxD)
SCLK period
TxD data to SCLK rise or fall*
TxD data hold after SCLK rise or fall* t
RxD data valid to SCLK rise or fall*
RxD data hold after SCLK rise or fall* t
SCLK period (programmable)
TxD data to SCLK rise
TxD data hold after SCLK rise
RxD data valid to SCK rise
RxD data hold after SCK rise
In the tables below, the letter x represents the fsys cycle period, which varies, depending on the
Parameter
Parameter
t
t
OSS
SRD
VALID
0
t
0
SCY
TMP1941AF-249
t
t
t
t
t
t
t
t
Symbol
Symbol
SCY
OSS
OHS
SRD
HSR
SCY
OSS
OHS
SRD
HSR
(t
VALID
SCY
1
(tSCY/2) − 15
(tSCY/2) − 15
(t
1
SCY
/2) − 5x − 23
2x + 8
x + 23
Min
Min
16x
16x
Equation
Equation
/2) + 3x
t
0
0
HSR
t
OHS
Max Min Max Min Max
Max Min Max Min Max
VALID
2
2
800
127
550
108
800
385
385
73
20 MHz
20 MHz
0
0
TMP1941AF
400
275
400
185
185
52
58
48
40 MHz
40 MHz
0
0
2003-03-27
VALID
3
3
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns