tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 6

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

TMP1941AF
8.
9.
10.
11.
7.7
7.8
7.9
7.10
7.11
7.12
8.1
8.2
8.3
9.1
9.2
9.3
10.1
10.2
10.3
10.4
10.5
10.6
11.1
11.2
8.1.1
8.1.2
8.2.1
8.2.2
8.2.3
8.2.4
8.3.1
8.3.2
8.3.3
9.1.1
9.1.2
10.2.1
10.2.2
10.2.3
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.3.7
10.3.8
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
10.4.7
10.5.1
External Bus Interface........................................................................................................................................... 66
Chip Select/Wait Controller .................................................................................................................................. 75
DMA Controller (DMAC)..................................................................................................................................... 84
8-Bit Timers (TMRAs)........................................................................................................................................ 109
Port 5 (P50–P57) ............................................................................................................................................. 47
Port 7 (P70–P77) ............................................................................................................................................. 48
Port 8 (P80–P87) ............................................................................................................................................. 52
Port 9 (P90–P97) ............................................................................................................................................. 55
Port A (PA0–PA7) ........................................................................................................................................... 60
Open-Drain Output Control ............................................................................................................................. 65
Address and Data Buses .................................................................................................................................. 67
External Bus Operation.................................................................................................................................... 68
Bus Arbitration ................................................................................................................................................ 73
Programming Chip Select Ranges ................................................................................................................... 75
Chip Select/Wait Control Registers ................................................................................................................. 81
Application Example ....................................................................................................................................... 83
Features............................................................................................................................................................ 84
Implementation ................................................................................................................................................ 85
Register Description ........................................................................................................................................ 87
Operation ......................................................................................................................................................... 97
DMA Transfer Timing................................................................................................................................... 106
Programming Example .................................................................................................................................. 108
Block Diagrams ............................................................................................................................................. 110
Timer Components ........................................................................................................................................ 112
Supported Configurations ....................................................................................................................... 67
States of the Address Bus During On-Chip Address Accesses ............................................................... 67
Basic Bus Operation ............................................................................................................................... 68
Wait Timing............................................................................................................................................ 69
ALE Pulse Width .................................................................................................................................... 71
Read Recovery Time............................................................................................................................... 72
Bus Access Control................................................................................................................................. 73
Bus Arbitration Flow .............................................................................................................................. 73
Relinquishing the bus.............................................................................................................................. 74
Base/Mask Address Registers (BMA0–BMA3) ..................................................................................... 75
Base Address and Address Mask Value Calculations ............................................................................. 78
On-Chip DMAC Interface....................................................................................................................... 85
DMAC Block.......................................................................................................................................... 86
Bus Snooping.......................................................................................................................................... 86
DMA Control Register (DCR) ................................................................................................................ 88
Channel Control Registers (CCRn)......................................................................................................... 89
Channel Status Registers (CSRn)............................................................................................................ 91
Source Address Registers (SARn) .......................................................................................................... 92
Destination Address Registers (DARn) .................................................................................................. 93
Byte Count Registers (BCRn) ................................................................................................................. 94
DMA Transfer Control Registers (DTCRn)............................................................................................ 95
Data Holding Register (DHR)................................................................................................................. 96
Overview................................................................................................................................................. 97
Transfer Request Generation ................................................................................................................ 100
DMA Address Modes ........................................................................................................................... 101
DMA Channel Operation ...................................................................................................................... 102
DMA Channel Priority.......................................................................................................................... 104
Interrupts............................................................................................................................................... 104
Data Packing and Unpacking ................................................................................................................ 105
Dual-Address Mode .............................................................................................................................. 106
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