aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 90

• Manufacturer Part Number: aduc7030
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

ADuC7030/ADuC7033
TIMER3 - WATCHDOG TIMER
Timer3 has two modes of operation, normal mode and
watchdog mode. The Watchdog timer is used to recover from
an illegal software state. Once enabled it requires periodic
servicing to prevent it from forcing a reset of the processor.
Timer3 reloads the value from T3LD either when TIMER3
overflows, or immediately when T3CLRI is written.
Normal mode:
The Timer3 in normal mode is identical to Timer0, in 16-bit
mode of operation, except for the clock source. The clock
source is the Low Power 32.768kHz oscillator and can be scaled
by a factor of 1, 16, or 256.
Watchdog mode:
Watchdog mode is entered by setting T3CON[5]. Timer3
decrements from the timeout value present in T3LD Register
until zero. The maximum timeout is 512 seconds, using the
maximum pre-scalar /256 and full-scale in T3LD.
User software should only configure a minimum timeout
period of 30msecs. This is to avoid any conflict with Flash/EE
memory page erase cycles, which require 20ms to complete a
single page erase cycle, and Kernel Execution.
Timer3 Interface:
Timer3 interface consists of four MMRS:
- T3CON is the configuration MMR described in Table 37
- T3LD and T3VAL are 16-bit registers (bit 0 to 15) and hold
16-bit unsigned integers. T3VAL is read-only.
- T3CLRI is an 8-bit register. Writing any value to this register
will clear the Timer3 interrupt in normal mode or will reset a
new timeout period in watchdog mode
LOW POWER
32.768kHz
PRESCALER
1, 16, 256
Figure 33. Timer3 Block Diagram
Rev. PrE | Page 90 of 150
UP/DOWN COUNTER
16-BIT LOAD
TIMER3
VALUE
16-BIT
If T3VAL reaches 0, a reset or an interrupt occurs, depending
on T3CON[1]. To avoid a reset or an interrupt event, any value
must be written to T3CLRI before T3VAL reaches zero. This
reloads the counter with T3LD and begins a new timeout
period.
Once watchdog mode is entered, T3LD and T3CON are write-
protected. These two registers can not be modified until a
Power On Reset event, resets the Watchdog Timer, after any
other reset event, the Watchdog Timer continues to count. The
Watchdog Timer should be configured in the initial lines of user
code to avoid an infinite loop of Watchdog Resets. User
software should only configure a minimum timeout period of
30msecs.
Timer3 is automatically halted during JTAG debug access and
will only recommence counting once JTAG has relinquished
control of the ARM7 core. By default, Timer3 continues to
count during power-down. This may be disabled by setting bit
zero in T3CON. It is recommended that the default value is
used, i.e. that the Watchdog Timer continues to count during
power-down.
Timer3 Load Register:
Name:
Address:
Default
Value:
Access:
Function:
T3LD
0xFFFF0360
0x0040
Read/Write
This 16-bit MMR holds the Timer3 reload value
WATCHDOG RESET
TIMER3 IRQ
Preliminary Technical Data