aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 24

• Manufacturer Part Number: aduc7030
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

ADuC7030/ADuC7033
The minimum latency for FIQ or IRQ interrupts is five cycles.
This consists of the shortest time the request can take through
the synchronizer plus the time to enter the exception mode.
Note that the ARM7TDMI will initially (1
ARM (32-bit) mode when an exception occurs. The user may
immediately switch from ARM mode to Thumb mode if
required, e.g. when executing interrupt service routines.
MEMORY ORGANISATION
The ARM7, a Von Neumann architecture, MCU core sees
memory as a linear array of 2
Figure 10 and Figure 11, the ADuC7030 and the ADuC7033
both map this into 4 distinct user areas namely, a re-mappable
memory area, an SRAM area, a Flash/EE area and a Memory
Mapped Register (MMR) area.
1.
2.
3.
4.
Any access, either reading or writing, to an area not defined in
the memory map will result in a Data Abort exception.
Memory Format
The ADuC7030/ADuC7033 memory organization is configured
in little endian format: the least significant byte is located in the
lowest byte address and the most significant byte in the highest
byte address.
For the ADuC7030,the first 30kBytes of this memory space
is used as an area into which the on-chip Flash/EE or
SRAM can be remapped.
For the ADuC7033, the first 94kBytes of this memory
space is used as an area into which the on-chip Flash/EE or
SRAM can be remapped.
Both the ADuC7030 and the ADuC7033, feature a second
4kByte area at the top of the memory map used to locate
the Memory Mapped Registers (MMR), through which all
on-chip peripherals are configured and monitored.
The ADuC7030 features a SRAM size of 4 kByte
The ADuC7033 features a SRAM size of 6 kByte
The ADuC7030 features 32 kByte of On-Chip Flash/EE
memory. 30kByte of On-Chip Flash/EE memory are
available to the user.
The ADuC7033 features 96 kByte of On-Chip Flash/EE
memory. 94kByte of On-Chip Flash/EE memory are
available to the user
For both the ADuC7030 and ADuC7033, 2 kBytes are
reserved for the on-chip Kernel.
BIT 31
BYTE 3
B
7
3
.
.
.
BYTE 2
Figure 9. Little Endian Format
A
6
2
.
.
.
32 BITS
BYTE 1
9
5
1
.
.
.
32
byte locations. As shown in
BYTE 0
8
4
0
.
.
.
BIT 0
st
instruction) run in
0xFFFFFFFFh
0x00000004h
0x00000000h
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SRAM
The ADuC7030 features 4kBytes of SRAM, organized as 1024 X
32 bits, i.e. 1024 Words, which is located at 0x40000.
The ADuC7033 features 6kBytes of SRAM, organized as 1536 X
32 bits, i.e. 1536 Words, which is located at 0x40000.
The RAM space can be used as data memory and also as a
volatile program space.
ARM code can run directly from SRAM at full clock speed
given that the SRAM array is configured as a 32-bit wide
memory array.
SRAM is read/writeable in 8-, 16-, 32-bit segments.
Remap
The ARM exception vectors are all situated at the bottom of the
memory array, from address 0x00000000 to address
0x00000020.
FFFF0000h
00080000h
00040000h
00000000h
FFFF0000h
00080000h
00040000h
00000000h
FFFF0FFFh
FFFF0FFFh
00087FFFh
00040FFFh
00007FFFh
00097FFFh
0017FFFh
00417FFh
Preliminary Technical Data
Figure 10. ADuC7030 Memory Map
Figure 11. ADuC7033 Memory Map
RESERVED
MMRs
RESERVED
FLASH/EE
RESERVED
SRAM
RESERVED
RE-MAPPABLE MEMORY SPACE
(FLASH/EE OR SRAM)
RESERVED
MMRs
RESERVED
FLASH/EE
RESERVED
SRAM
RESERVED
RE-MAPPABLE MEMORY SPACE
(FLASH/EE OR SRAM)