aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 26

• Manufacturer Part Number: aduc7030
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

ADuC7030/ADuC7033
ADUC7030/ADUC7033 RESET
There are four kinds of reset: external reset, Power-on-reset, watchdog reset and software reset. The RSTSTA register indicates the source
of the last reset and can also be written by user code to initiate a software reset event. The bits in this register can be cleared to ‘0’ by
writing to the RSTCLR MMR at 0xFFFF0234. The bit designations in RSTCLR mirror those of RSTSTA. These registers can be used
during a reset exception service routine to identify the source of the reset. The implications of all four kinds of reset event are tabulated in
Table 11 below.
Table 11. Device RESET Implications
RESET
POR
Watchdog Reset
Software Reset
External Reset Pin
Note 1: If LVF is enabled(HVCFG0[2]), RAM has not been corrupted by the POR reset mechanism if LVF Status bit HVSTA[6] is ‘1’ .
RSTSTA Register:
Name:
Address:
Default
Value:
Access:
Function:
Table 12. RSTSTA/RSTCLR MMR Bit Designations
Note:
Bit
7 to 4
3
2
1
0
If the "Software Reset" bit in RSTSTA is set, any write to RSTCLR that does not clear this bit will generate a software reset
IMPACT
Description
Not Used
These bits are not used and will always read as ‘0’
External Reset
Set to 1 automatically when an external reset occurs
Cleared by setting the corresponding bit in RSTCLR
Software Reset
Set to ‘1’ by user code to generate a software reset.
Cleared by setting the corresponding bit in RSTCLR
Watchdog timeout
Set to 1 automatically when a watchdog timeout occurs
Cleared by setting the corresponding bit in RSTCLR
Power-on-reset
Set automatically when a power-on-reset occurs
Cleared by setting the corresponding bit in RSTCLR
RSTSTA
0xFFFF0230
Depends on type of reset
Read/Write Access
This 8-bit register indicates the source of the last
reset event and can also be written by user code
to initiate a software reset.
Reset
External
Pins to
Default
State
Kernel
Executed
Reset All External
MMRs(excluding
RSTSTA
Rev. Pre | Page 26 of 150
Reset All
HV
Indirect
Registers
Name:
Address:
Access:
Function:
RSTCLR Register:
Peripherals
Reset
RSTCLR
0xFFFF0234
Write Only
This 8-bit write only register clears the
corresponding bit in RSTSTA.
Preliminary Technical Data
Watchdog
Timer
Reset
RAM
Valid
Note 1
RSTSTA
(Status after
Reset Event)
RSTSTA[0] =1
RSTSTA[1] =1
RSTSTA[2] =1
RSTSTA[3] =1