aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 135

• Manufacturer Part Number: aduc7030
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Bit
7
6
5
4
3
2
1
0
Description
after user code switches from BSD Write Mode to BSD Read Mode. A Stop Condition interrupt could be used to ensure that this
scenario is avoided.
Sync Timer Stop Edge Type Bit
This bit is cleared to 0 by user code to stop the sync timer on the falling edge count configured via the LHSCON1[7:4] register.
This bit is set to 1 by user code to stop the sync timer on the rising edge count configured via the LHSCON1[7:4] register.
Mode of Operation Bit
This bit is cleared to 0 by user code to select LIN mode of operation
This bit is set to 1 by user code to select BSD mode of operation
Enable Compare Interrupt Bit
This bit is cleared to 0 by user code to disable compare interrupts
This bit is set to 1 by user code to generate an LHS Interrupt(IRQEN[7]) when the value in LHSVAL0 (LIN Synchronisation Bit
Timer) = the value in the LHSCMP register. The LHS Compare Interrupt bit LHSSTA[3] is set when this interrupt occurs. This
configuration is used in BSD write mode to allow user code correctly time the output pulse widths of BSD bits to be transmitted.
Enable Stop Interrupt
This bit is cleared to 0 by user code to disable interrupts when a stop condition occurs
This bit is set to 1 by user code to generate an interrupt when a stop condition occurs
Enable Start Interrupt
This bit is cleared to 0 by user code to disable interrupts when a start condition occurs
This bit is set to 1 by user code to generate an interrupt when a start condition occurs
LIN Sync Enable Bit
This bit is cleared to 0 by user code to disable LHS functionality
This bit is set to 1 by user code to enable LHS functionality
Edge Counter Clear Bit
This bit is set to 1 by user code to clear the internal edge counters in the LHS peripheral.
This bit is cleared to 0 automatically after a 15us delay.
LHS Reset Bit
This bit is set to 1 by user code to reset all LHS logic to default conditions.
This bit is cleared to 0 automatically after a 15us delay.
Rev. PrE | Page 135 of 150
ADuC7030/ADuC7033