aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 73

• Manufacturer Part Number: aduc7030
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
ADUC7030/ADUC7033 SYSTEM CLOCKS
The ADuC7030/ADuC7033 integrates a highly flexible clocking
system, which may be clocked from one of three sources:
- An integrated on-chip precision oscillator
- An integrated on-chip low power oscillator
- An external watch crystal
These three options are shown in Figure 27.
Each of the internal oscillators are divided by 4 to generate a
clock frequency of 32.768kHz. The PLL locks onto a multiple
(625) of 32.768kHz, supplied by either of the internal oscillators
or the external crystal, to provide a stable 20.48MHz clock for
the system. The core can operate at this frequency, or at binary
submultiples of it, which allows power saving if peak
performance is not required.
OSCILLATOR
PRECISION
CLOCK
CORE
CORE CLOCK
PLL OUTPUT
(20.48MHz)
1
8
PLL LOCK
PRECISION
MCU
131kHz
2
DIV 4
CD
1
EXTERNAL
32.768kHz
SPI
PRECISION
32.768kHz
Figure 27. ADuC7030/ADuC7033 System Clock Generation
EXTERNAL CRYSTAL
CONTROLLER
PLL OUTPUT
(OPTIONAL)
CIRCUITRY
CRYSTAL
20.48MHz
PLLCON
FLASH
CORE CLOCK
PLL
LOW POWER
32.768kHz
OSCILLATOR
LOW POWER
Rev. PrE | Page 73 of 150
ECLK 2.5MHz
CLOCK
ADC
DIVIDER
CLOCK
LOW POWER
UART
131kHz
ADCMDE
DIV 4
ADC
By default, the PLL is driven by the Low Power oscillator which
generates a 20.48MHz clock source. The ARM7TDMI Core, is
driven by a CD divided clock derived from the output of the
PLL. By default, the CD divider is configured to divide the PLL
output by 2, which generates a core clock of 10.24MHz. The
divide factor may be modified to generate a binary weighted
divider factor from 1 to 128, which may be altered dynamically
by user code.
The ADC is driven by the output of the PLL, divided to give an
ADC clock source of 512kHz. In low-power mode the ADC
clock source is switched from the standard 512kHz to the Low
Power 131kHz oscillator.
It should also be noted that the low power oscillator drives both
the watchdog and core wake-up timers through a divide by 4
circuit. A detailed block diagram of the ADuC7030/ADuC7033
clocking system is shown in Figure 27.
CORE CLOCK
CORE CLOCK
CORE CLOCK
CORE CLOCK
OSCILLATOR
LOW POWER
LOW POWER
LOW POWER
LOW POWER
LOW POWER
LOW POWER
LOW POWER
PLL OUTPUT
PRECISION
PRECISION
PRECISION
EXTERNAL
EXTERNAL
EXTERNAL
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
131kHz
GPIO_5
GPIO_8
(5MHz)
SYNCHRONIZATION
HIGH ACCURCY
CALIBRATION
CALIBRATION
LOW POWER
WATCHDOG
COUNTER
COUNTER
LIFE TIME
WAKE-UP
TIMER 0
TIMER 1
TIMER 2
TIMER 3
TIMER 4
LIN H/W
ADuC7030/ADuC7033
STI