aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 112

• Manufacturer Part Number: aduc7030
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

ADuC7030/ADuC7033
High Voltage Configuration1 Register:
Name:
Address:
Default Value:
Access:
Function:
Table 69. HVCFG1 Bit Designations
Bit
7
6
5
4
3
2
1
0
Description
Attenuator Enable Bit
This bit is cleared to 0 to disable the internal voltage attenuator and attenuator buffer.
This bit is set to 1 to enable the internal voltage attenuator and attenuator buffer.
High Voltage Temperature Monitor
The high voltage temperature monitor is an un-calibrated temperature monitor located on-chip close to the high voltage
circuits. This monitor is completely separate to the on-chip, precision temperature sensor (controlled via ADC1CON[7,6]) and
allows user code to monitor die temperature change close the hottest part of the ADuC7030/ADuC7033 die. The monitor
generates a typical output voltage of 600mV at 25qC and has a negative temperature coefficient of typically -2.1mV/qC
This bit is set to 1 to enable the on-chip, high voltage temperature monitor. Once enabled this voltage out temperature monitor
is routed directly to the voltage channel ADC.
This bit is cleared to 0 to disable the on-chip, high voltage temperature monitor.
Voltage Channel Short Enable Bit
This bit is set to 1 to enable an internal short (at the attenuator, before ADC input buffer) on the voltage channel ADC and allow
noise be measured as a self-diagnostic test.
This bit is cleared to 0 to disable an internal short on the voltage channel.
WU and STI Read Back Enable Bit
This bit is cleared to 0 to disable input capability on the external WU/STI pin
This bit is set to 1 to enable input capability on the external WU/STI pin. In this mode, a rising or falling edge transition on the
WU/STI pin will generate a high voltage interrupt. Once this bit is set, the state of the WU/STI pin can be monitored via the
HVMON register (HVMON[7] and HVMON[5]).
HV-IO Driver Enable Bit
This bit is set to 1 to re-enable any High Voltage-IO pins (LIN/BSD/STI/WU) that have been disabled as a result of an short circuit
current event(event must last longer than 20µsecs for LIN/BSD/STI Pins and 400usecs for WU Pin).
This bit must also be set to 1 to re-enable the WU/STI pins if disabled by a thermal event.
It should be noted that this bit must be set to clear any pending interrupt generated by the short circuit event (even if the event
has passed) as well as re-enabling the High-Voltage IO pins.
This bit is cleared to 0 automatically.
Enable/Disable Short Circuit Protection (LIN/BSD & STI)
This bit is set to 1 to enable ‘passive’ short circuit protection on LIN pin. In this mode, a short circuit event on the LIN/BSD pin
will generate a HV interrupt (IRQ3-IRQEN[16]), assert the appropriate status bit in HVSTA but will NOT disable the short circuiting
pin.
This bit is cleared to 0 to enable ‘active’ short circuit protection on LIN/BSD pin. In this mode, a short circuit event the LIN/BSD
pin will generate a HV interrupt (IRQ3-IRQEN[16]), assert the appropriate status bit in HVSTA and automatically disable the short
circuiting pin. Once disabled, the I/O pin can only be re-enabled by writing to HVCFG1[3].
WU Pin Time-Out ( MonoFlop ) Counter Enable/Disable
This bit is set to disable the WU I/O time-out counter.
This bit is cleared to enable a time-out counter which automatically de-asserts the WU pin 1.3 seconds after user code has
asserted the WU pin via HVCFG0[4].
WU O/C Diagnostic Enable
This bit is set to enable an internal WU I/O diagnostic pull-up resistor to the VDD pin thus allowing detection of an O/C condition
on the WU pin.
This bit is cleared to disable an internal WU I/O diagnostic pull-up resistor
HVCFG1
Indirectly addressed via the HVCON high voltage interface
0x00
Read/Write
This 8-bit register controls the function of high voltage circuits on the ADuC7030/ADuC7033. This register is not an
MMR and does not appear in the MMR memory map. It is accessed via the HVCON registered interface, data to be
written to this register is loaded via HVDAT and data is read back from this register via HVDAT.
Rev. PrE | Page 112 of 150
Preliminary Technical Data