aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 23

• Manufacturer Part Number: aduc7030
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
ARM7 Exceptions
The ARM7 supports five types of exceptions, with a privileged
processing mode associated with each type. The five types of
exceptions are
x
x
x
x
x
Typically, the programmer defines interrupts as IRQ, but for
higher priority interrupts, the programmer can define
interrupts as of type FIQ.
The priority of these exceptions and vector address are listed in
Table 9.
Table 9.
Priority
1
2
3
4
5
6
6
1
The list of exceptions in Table 9.are located from 0x00 to 0x1C,
with a reserved location at 0x14. This location is required to be
written with either 0x27011970 or the checksum of Page Zero,
excluding location 0x14. If this is not done, user code does not
execute and LIN download mode is entered. For more
information, refer to the relevant LIN download Technote.
ARM Registers
The ARM7TDMI has 16 standard registers. R0-R12 are used for
data manipulation, R13 is the stack pointer, R14 is the link
register and R15 is the program counter which indicates the
instruction currently being executed. The link register contains
the address from which the user has branched, if the branch and
link command was used, or the command during which an
exception occurred.
The stack pointer contains the current location of the stack. As
a general rule of thumb on an ARM7TDMI, the stack starts at
the top of the available RAM area, and descends, using the area
as required. A separate stack is defined for each of the
exceptions. The size of each stack is user configurable and is
dependent on the target application. On the ADuC7030/
ADuC7033 the stack begins at 0x00040FFC and descends.
When programming using high level languages, such as C, it
A software interrupt and an undefined instruction exception have the same
priority and are mutually exclusive.
Normal interrupt or IRQ. It is provided to service general-
purpose interrupt handling of internal and external events.
Fast interrupt or FIQ. It is provided to service data transfer
or communication channel with low latency. FIQ has
priority over IRQ.
Memory abort (prefetch and data).
Attempted execution of an undefined instruction.
Software interrupt (SWI) instruction that can be used to
make a call to an operating system.
Exception
Hardware Reset
Memory Abort (Data)
FIQ
IRQ
Memory Abort (Prefetch)
Software Interrupt
Undefined Instruction
1
1
Address
0x00
0x10
0x1C
0x18
0x0C
0x08
0x04
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can be possible to ensure that the stack does not overflow. This
is dependent on the compiler used.
When an exception occurs, some of the standard register are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the
stack pointer (R13) and the link register (R14) as represented in
Figure 2. The FIQ mode has more registers (R8 to R12)
supporting faster interrupt processing. With the increased
number of non-critical registers, the interrupt may be processed
without the need to save or restore these registers, which
reduces the response time of the interrupt handling process.
More information relative to the programmer’s model and the
ARM7TDMI core architecture can be found in the following
documents available from ARM Ltd.:
DDI0029G, ARM7TDMI Technical Reference Manual.
DDI0100E, ARM Architecture Reference Manual.
Interrupt Latency
The worst case latency for an FIQ consists of the longest time
the request can take to pass through the synchronizer, plus the
time for the longest instruction to complete (the longest
instruction is an LDM) which loads all the registers including
the PC, plus the time for the data abort entry, plus the time for
FIQ entry. At the end of this time, the ARM7TDMI will be
executing the instruction at 0x1C (FIQ interrupt vector
address). The maximum total time is 50 processor cycles, which
is just over 2.44 μS in a system using a continuous 20.48 MHz
processor clock. The maximum IRQ latency calculation is
similar, but must allow for the fact that FIQ has higher priority
and could delay entry into the IRQ handling routine for an
arbitrary length of time. This time may be reduced to 42 cycles
if the LDM command is not used, some compilers have an
option to compile without using this command. Another option
is to run the part in THUMB mode where this is reduced to
22 cycles.
USER MODE
R15 (PC)
CPSR
R10
R11
R12
R13
R14
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
Figure 8. ADuC7030/ADuC7033 Register Organization
SPSR_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
R8_FIQ
R9_FIQ
MODE
FIQ
SPSR_SVC
R13_SVC
R14_SVC
MODE
SVC
ADuC7030/ADuC7033
SPSR_ABT
R13_ABT
R14_ABT
ABORT
MODE
USABLE IN USER MODE
SYSTEM MODES ONLY
SPSR_IRQ
R13_IRQ
R14_IRQ
MODE
IRQ
UNDEFINED
SPSR_UND
R13_UND
R14_UND
MODE