aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 80

• Manufacturer Part Number: aduc7030
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

ADuC7030/ADuC7033
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 16 interrupt sources on the ADuC7030/ADuC7033,
which are controlled by the Interrupt Controller. Most
interrupts are generated from the on-chip peripherals such as
the ADC, UART, etc.. The ARM7TDMI CPU core will only
recognize interrupts as one of two types, a normal interrupt
request IRQ and a fast interrupt request FIQ. All the interrupts
can be masked separately.
The control and configuration of the interrupt system is
managed through nine interrupt-related registers, four
dedicated to IRQ, four dedicated to FIQ. An additional MMR is
used to select the programmed interrupt source. The bits in
each IRQ and FIQ registers represent the same interrupt source
as described in Table 44.
IRQSTA/FIQSTA should be saved immediately upon entering
the ISR (Interrupt Service Routine) to ensure that all valid
interrupt sources are serviced.
The interrupt generation route through the ARM7TDMI core is
shown in Figure 29.
Table 44. IRQ/FIQ MMRs bit description
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Description
All interrupts OR’ed
SWI:
not used in IRQEN/CLR and FIQEN/CLR
Timer 0
Timer 1
Timer 2 - Wake Up timer
Timer 3 - Watchdog Timer
Timer 4 - STI Timer
LIN Hardware
Flash/EE Interrupt
PLL Lock
ADC
UART
SPI
XIRQ0 ( GPIO IRQ 0 )
XIRQ1 ( GPIO IRQ 1 )
Reserved
IRQ3 High Voltage IRQ
Reserved
XIRQ4 ( GPIO IRQ 4 )
XIRQ5 ( GPIO IRQ 5 )
Rev. PrE | Page 80 of 150
For more information please refer to:
Timer0—Life-Time timer
Timer1
Timer2 - Wake-Up Timer
Timer3 - Watchdog Timer
Timer4 - STI Timer
LIN (Local Interconnect NETWORK) INTERFACE
ADuC7030 Flash/EE Control Interface
ADuC7030/ADuC7033 System Clocks
16-Bit 6' Analog to Digital Converters
UART SERIAL INTERFACE
SERIAL PERIPHERAL INTERFACE
High Voltage Interrupt
Consider the example of Timer0, which is configured to
generate a timeout every 1ms.
After the first 1ms timeout, FIQSIG/IRQSIG[2] will be set and
will only be cleared by writing to T0CLRI.
If Timer0 is not enabled in either IRQEN or FIQEN, then
FIQSTA/IRQSTA[2] will not be set and an interrupt will not
occur.
If Timer0 is enabled in either IRQEN or FIQEN, then either
FIQSTA/IRQSTA[2] will be set and either an FIQ or an IRQ
interrupt will occur.
Please note that the IRQ and FIQ interrupt bit definitions in the
CPSR only control interrupt recognition by the ARM Core, not
by the peripherals.
For example, if Timer2 is configured to generate an IRQ via
IRQEN, the IRQ interrupt bit is set (Disabled) in the CPSR and
the ADuC7030 is powered down. When an interrupt occurs,
the peripherals will be woken, but the ARM core will remain
powered down. This is equivalent to POWCON = 0x71. The
ARM Core can only be powered up by a reset event if this
occurs.
Preliminary Technical Data