aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 67

• Manufacturer Part Number: aduc7030
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
ADC Low Power-Plus Mode
In Low Power-Plus mode, the I-ADC channel is enabled in a
mode almost identical to low-power mode (ADCMDE[4:3]).
However, in this mode, the I-ADC gain is fixed at 512 and the
ADC consumes an additional 200µA (approx.) to yield
improved noise performance relative to the low-power mode
setting.
Again, all of the ADC peripheral functions (result counter,
digital comparator and accumulator) described earlier in
normal power mode can still be enabled in Low Power-Plus
mode.
As in Low Power Mode, the I-ADC only, is configured to run at
a low update rate, continuously monitoring battery current. The
MCU will be in power-down mode and will only be woken up
when the I-ADC interrupts the MCU. This would happen after
the I-ADC detects a current conversion result beyond a pre-
programmed threshold or set-point.
It is also possible to select either the ADC Precision Voltage
Reference or the ADC Low Power Mode Voltage Reference via
ADCMDE[5].
ADC comparator and accumulator
Every I-ADC result can also compared to a pre-set threshold
level (ADC0TH) as configured via ADCCFG[4:3]. An MCU
interrupt is generated if the absolute (sign-independent) value
of the ADC result is greater than the pre-programmed
comparator threshold level. An extended function of this
comparator function allows user code to configure a threshold
counter (ADC0THV) which monitors the number of I-ADC
results that have occurred above or below the pre-set threshold
level. Again, an ADC interrupt is generated once the threshold
counter reaches a pre-set value (ADC0TCL).
Finally, a 32-bit accumulator(ADC0ACC) function can be
configured(ADCCFG[6:5]) allowing the I-ADC to add(or
subtract) multiple I-ADC sample results. User code to read the
accumulated value directly(ADC0ACC) without any further
software processing.
ADC Sinc3 Digital Filter Response
The overall frequency response on all ADuC7030/ADuC7033’s
ADCs is dominated by the low pass filter response of the on-
chip Sinc3 digital filters. The Sinc3 filters are used to decimate
the ADC sigma-delta modulator output data bit-stream to
generate a valid 16-bit data result. The digital filter response is
identical for all ADCs and is configured via the 16-bit ADC
Filter (ADCFLT) register, which determines the overall
throughput rate of the ADCs. The noise resolution of the ADCs
is determined by the programmed ADC throughput rate. In the
case of the Current Channel ADC, the noise resolution will be
determined by throughput rate and selected gain.
Rev. PrE | Page 67 of 150
The overall frequency response and the ADC through-put is
dominated by the configuration of the Sinc3 Filter Decimation
Factor (SF) bits (ADCFLT[6:0]) and the Averaging Factor (AF)
bits(ADCFLT[13:8]). Due to limitations on the digital filter
internal data-path, there are some limitations on the allowable
combinations of SF(Sinc3 Decimation Factor) and
AF(Averaging Factor) that can be used to generate a required
ADC output rate. This restriction limits the minimum ADC
update in Normal Power Mode to 4Hz or 1Hz in Low Power
Mode. The calculation of the ADC throughput rate is detailed
in the ADCFLT bit designations table and the restrictions on
allowable combinations of AF and SF values are outlined again
in Table 36.
Table 36. Allowable Combinations of SF and AF
SF
0-31
32-63
64-127
By default the ADCFLT = 0x07 which configures the ADCs for
a through-put of 1.0KHz with all other filtering options (Chop,
Running Average, Averaging Factor and Sin3 Modify) being
disabled. A typical filter response based on this default
configuration is shown in Figure 19 below.
An additional ‘Sinc3 Modify’ bit (ADCFLT[7]) is also available
in the ADCFLT register. This bit is set by user code to modify
the standard Sinc3 frequency response increasing the filter stop-
band rejection by 5dBs approx. This is achieved by inserting a
second notch (NOTCH2) at FNOTCH2 = 1.333 X FNOTCH
where FNOTCH is the location of the 1st notch in the response.
There is a slight increase in ADC noise if this bit is active.
Figure 20 shows the modified 1KHz filter response when the
Sinc3 modify bit is active. The ‘new’ notch is clearly visible at
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
AF Range
0
Figure 19. Typical Digital Filter Response at FADC=1.0kHz
500
1000 1500 2000 2500 3000 3500 4000 4500 5000
0
FREQUENCY (kHz)
(ADCFLT = 0x0007)
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