aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 124

• Manufacturer Part Number: aduc7030
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

ADuC7030/ADuC7033
SERIAL PERIPHERAL INTERFACE
The ADuC7030 features a complete hardware Serial Peripheral
Interface (SPI) on-chip. SPI is an industry standard
synchronous serial interface, which allows eight bits of data to
be synchronously transmitted and received simultaneously, i.e.,
full duplex.
The SPI interface is only operational with core clock divider bits
(POWCON[2:0]= 0 or 1).
The SPI Port can be configured for Master or Slave operation
and consists of four pins, which are multiplexed with four
GPIO. The four SPI pins are MISO, MOSI, SCLK and SS . The
pins to which this signals are connected are shown in Table 81.
Table 81. SPI Output Pins
Pin
GP0 ( GPIO MODE 1 )
GP1 ( GPIO MODE 1 )
GP2 ( GPIO MODE 1 )
GP3 ( GPIO MODE 1 )
MISO (Master In, Slave Out Data I/O Pin)
The MISO (master in slave out) pin is configured as an input
line in master mode and an output line in slave mode. The
MISO line on the master (data in) should be connected to the
MISO line in the slave device (data out). The data is transferred
as byte wide (8-bit) serial data, MSB first.
MOSI (Master Out, Slave In Pin)
The MOSI (master out slave in) pin is configured as an output
line in master mode and an input line in slave mode.
The MOSI line on the master (data out) should be connected to
the MOSI line in the slave device (data in). The data is
transferred as byte wide (8-bit) serial data, MSB first.
SCLK (Serial Clock I/O Pin)
The master serial clock (SCLK) is used to synchronize the data
being transmitted and received through the MOSI SCLK
period. Therefore, a byte is transmitted/received after eight
SCLK periods. The SCLK pin is configured as an output in
master mode and as an input in slave mode.
In master mode polarity and phase of the clock are controlled
by the SPICON register, and the bit-rate is defined in the
SPIDIV register as follow:
Signal
SS
SCLK
MISO
MOSI
Description
Chip Select
Serial Clock
Master Out, Slave In
Master In, Slave Out
Rev. PrE | Page 124 of 150
The maximum speed of the SPI clock is dependant on the clock
divider bits and is summarized in Table 82.
Table 82. SPI speed vs. clock divider bits in master mode
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 5.12 Mb at CD = 0.
The formula to determine the maximum speed is as follow:
In both master and slave modes, data is transmitted on one edge
of the SCL signal and sampled on the other. Therefore, it is
important that the polarity and phase are configured the same
for the master and slave devices.
Chip Select ( SS ) Input Pin
In SPI Slave Mode, a transfer is initiated by the assertion of SS
which is an active low input signal. The SPI port will then
transmit and receive 8-bit data until the transfer is concluded by
de-assertion of SS . In slave mode SS is always an input.
SPI registers definition
The following MMR registers are used to control the SPI
interface:
- SPICON: 16-bit control register
- SPISTA: 8-bit read only status register
- SPIDIV: 8-bit serial clock divider register
- SPITX: 8-bit write only transmit register
- SPIRX: 8-bit read only receive register
f
f
serialcloc
serialcloc
CD bits
SPIDIV
Max SCLK (MHz)
k
k
Equation 1. SPI Baud Rate Calculation
Preliminary Technical Data
2
u
f
20
HCLK
1 (
4
.

48
SPIDIV
MHz
0
0x05
1.667
)
1
0x0B
0.833