aduc7030 Analog Devices, Inc., aduc7030 Datasheet - Page 27

• Manufacturer Part Number: aduc7030
• Description: Integrated Precision Battery Sensor For Automotive
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
FLASH/EE MEMORY AND THE
ADUC7030/ADUC7033
The ADuC7030/ADuC7033 incorporate Flash/EE memory
technology on-chip to provide the user with nonvolatile, in-
circuit reprogrammable memory space.
Like EEPROM, Flash memory can be programmed in-system at
a byte level, although it must first be erased; the erase being
performed in page blocks. Thus, Flash memory is often and
more correctly referred to as Flash/EE memory.
Overall, Flash/EE memory represents a step closer to the ideal
memory device that includes nonvolatility, in-circuit program-
mability, high density, and low cost. Incorporated in the
ADuC7030/ADuC7033, Flash/EE memory technology allows
the user to update program code space in-circuit, without the
need to replace one time programmable (OTP) devices at
remote operating nodes.
The Flash/EE memory is physically located at 0x80000. Upon a
hard reset, it logically maps to 0x00000000. The factory default
contents of all Flash/EE memory locations is 0xFF. Flash/EE can
be read in 8/16/32 bit segments, and written in segments of 16
bits. The Flash/EE is rated for 10K endurance cycles. This rating
is based on the number of times that each individual byte is
cycled i.e. erased and programmed. A redundancy scheme may
be implemented in software to ensure greater than 10K cycles
endurance.
The user can also write data variables to the Flash/EE memory
during run-time code execution, for example, for storing
diagnostic battery parameter data.
The entire Flash/EE is available to the user as code and non-
volatile data memory. There is no distinction between data and
program, as ARM code shares the same space. The real width of
the Flash/EE memory is 16 bits, meaning that in ARM mode
(32-bit instruction), two accesses to the Flash/EE are necessary
for each instruction fetch. When operating at speeds less than
20.48 MHz the Flash/EE memory controller can transparently
fetch the second 16-bit half word (part of the 32-bit ARM op-
code) within a single core clock period. It is, therefore,
recommended that for speeds less than 20.48 MHz, that is, CD
> 0, that ARM mode is used. For 20.48MHz operation, that is,
CD = 0 , it is recommended to operate in thumb mode.
FEE0STA:
FEE0MOD:
FEE0CON:
FEE0DAT:
FEE0ADR:
FEE0SIG:
read only register, reflects the status of the Flash/EE control interface
sets the operating mode of the Flash/EE control interface
8-bit command register. The commands are interpreted as described in Table 13.
16-bit data register.
16-bit address register.
Holds the 24-bit code signature as a result of the signature command being initiated.
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The page size of this Flash/EE memory is 512 bytes. Typically, it
takes the Flash/EE controller 20 ms to erase a page, irrespective
of CD. To write a 16-bit word at CD = 0, 1, 2, 3 requires 50 μs;
70 μs at CD=4, 5; 80 μs at CD=6; and 105 μs at CD=7.
It is possible to write to a single 16 bit location only twice
between erases, that is, it is possible to walk bytes, not bits. If a
location is written to more than twice, then it is possible that
the contents of the Flash/EE page may be corrupted.
The Flash/EE memory can be programmed in-circuit, using a
serial download mode via the LIN interface or the integrated
JTAG port.
(1) Serial Downloading (In-Circuit Programming)
The ADuC7030/ADuC7033 facilitate code download via the
LIN pin. For more information please refer to the
ADuC7030/ADuC7033 LIN download protocol technote.
(2) JTAG access
The ADuC7030/ADuC7033 feature an on-chip JTAG debug
port to facilitate code download and debug.
ADuC7030 Flash/EE Memory
The total 32kBytes of Flash/EE are organized as 15k X 16 bits.
30kBytes are user space and 2kBytes are reserved for boot
loader/kernel space.
ADuC7033 Flash/EE Memory
The total 96kBytes of Flash/EE are organized as 47k X 16 bits.
94kBytes user space and 2kBytes reserved for boot
loader/kernel space.
ADUC7030 FLASH/EE CONTROL INTERFACE
The access to and control of the Flash/EE memory on the
ADuC7030 is managed by an on-chip memory controller. The
controller manages the Flash/EE memory as single block of
32 kbytes.
It should be noted that MCU core is halted until the command
is completed. User software must ensure that the Flash/EE
controller has completed any erase or write cycle before the PLL
is powered down. If the PLL is powered down before an erase or
write cycle is completed, the Flash/EE page can be corrupted.
User Code, LIN and JTAG programming use the Flash/EE
Control Interface, consists of the following MMRs:
ADuC7030/ADuC7033