peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 9
peb20532
Manufacturer Part Number
peb20532
Description
2 Channel Serial Optimized Communication Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB20532.pdf
(282 pages)
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List of Figures
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Data Sheet
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
System Integration With External DMA Controller . . . . . . . . . . . . . . . . 23
Point-to-Point Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Point-to-Multipoint Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 25
Multimaster Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Pin Configuration P-TQFP-100-3 Package . . . . . . . . . . . . . . . . . . . . . 27
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SCC Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SCC Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
XFIFO/RFIFO Word Access (Intel Mode) . . . . . . . . . . . . . . . . . . . . . . 45
XFIFO/RFIFO Word Access (Motorola Mode) . . . . . . . . . . . . . . . . . . . 45
Clock Supply Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Clock Mode 0a/0b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Clock Mode 1 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Clock Mode 2a/2b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Clock Mode 3a/3b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Clock Mode 4 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Selecting one time-slot of programmable delay and width . . . . . . . . . 56
Selecting one or more time-slots of 8-bit width . . . . . . . . . . . . . . . . . . 58
Clock Mode 5a Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Clock Mode 5a "Continuous Mode" . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Clock Mode 5a "Non Continuous Mode" . . . . . . . . . . . . . . . . . . . . . . . 61
Selecting one or more octet wide time-slots . . . . . . . . . . . . . . . . . . . . 63
Clock Mode 5b Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Clock Mode 6a/6b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Clock Mode 7a/7b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Enabled) . . . 69
DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Disabled) . . . 69
DPLL Algorithm for FM0, FM1 and Manchester Encoding . . . . . . . . . 70
Request-to-Send in Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
NRZ and NRZI Data Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
FM0 and FM1 Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Manchester Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
RTS/CTS Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SCC Test Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
HDLC Receive Data Processing in 16 bit Automode . . . . . . . . . . . . . . 85
HDLC Receive Data Processing in 8 bit Automode . . . . . . . . . . . . . . . 85
HDLC Receive Data Processing in Address Mode 2 (16 bit). . . . . . . . 86
HDLC Receive Data Processing in Address Mode 2 (8 bit). . . . . . . . . 86
HDLC Receive Data Processing in Address Mode 1 . . . . . . . . . . . . . . 86
9
PEB 20532
PEF 20532
2000-09-14
Page
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