peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 138

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

Data Sheet
5.2.2
Each register description is organized in three parts:
• a head with general information about reset value, access type (read/write), channel
• a table containing the bit information (name of bit positions) distinguished for the three
• a section containing the detailed description of each bit; the corresponding modes, the
Register 15
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Register 16
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Bit
Bit
specific offset addresses and usual handling;
major protocol modes HDLC/PPP (H), ASYNC (A) and BISYNC (B);
bit is valid for, are marked again by a bracket term right beside the full bit name.
7
7
Channel Specific SCC Registers
FIFOL
Receive/Transmit FIFO (Low Byte)
FIFOH
Receive/Transmit FIFO (High Byte)
6
6
read/write
-
Channel A
10
XFIFO: written by CPU, evaluated by SEROCCO-M
RFIFO: written by SEROCCO-M, evaluated by CPU
read/write
-
Channel A
11
XFIFO: written by CPU, evaluated by SEROCCO-M
RFIFO: written by SEROCCO-M, evaluated by CPU
H
H
5
5
RFIFO/XFIFO Access High Byte
RFIFO/XFIFO Access Low Byte
Channel B
60
Channel B
61
H
H
5-138
4
4
FIFO(15:8)
FIFO(7:0)
3
3
Register Description (FIFOL)
2
2
1
1
PEB 20532
PEF 20532
2000-09-14
0
0