peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 247

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

Figure 56
6.2.2
Also 2 ´
direction.
There are different interrupt indications concerned with the reception of data:
HDLC/SDLC/PPP
•
•
In addition to the message end (’RME’) interrupt the following information about the
received packet is stored by SEROCCO-M in special registers and/or RFIFO:
Data Sheet
’
with the receive FIFO threshold in register CCR3H, bit field ’RFTH(1..0)’; default is 32
bytes) can be read from RFIFO and the received message is not yet complete.
’
is completed, i.e. either
- one message which fits into RFIFO not exceeding the receive FIFO threshold, or
- the last part of a message, all in all exceeding the receive FIFO threshold
is stored in the RFIFO.
RPF’ (Receive Pool Full) interrupt, indicating that a specified number of bytes (limited
RME’ (Receive Message End) interrupt, indicating that the reception of one message

32 byte FIFO buffers (receive pools) are provided for each channel in receive
Transmit serial
Data Reception (Interrupt Driven)
data
Interrupt Driven Data Transmission (Flow Diagram)
Issue Command
CMDRL.XIF
CMDRL.XF
or
No
Reset Transmitter
End of Message
(CMDRL.XRES)
(up to 32 bytes)
'XPR' Interrupt
Write Data to
READY
START
XFIFO
XFIFO
247
?
Yes
CMDRL.XIF+.XME
CMDRL.XF+.XME
Issue Command
or
Transmit serial
append trailer
Action taken
by CPU
Interrupt
indication to CPU
Action taken
by the SCC
data and
Programming
PEB 20532
PEF 20532
2000-09-14