peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 100

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

PEB 20532
PEF 20532
Detailed Protocol Description
Transmission via this register is possible even when the transmitter is in XOFF state
(however, CTS must be ‘low’).
The ’TIC’ value is an eight-bit value. The number of significant bits is determined by the
programmed asynch character length via bit field ’CHL’ in register
CCR3L
. Parity value
(if programmed) and selected number of stop bits are automatically appended, equal to
the characters provided via the transmit data buffer. The usage of ’TIC’ is independent
of in-band flow control mechanism, i.e. is not affected by bit ’FLON’ in register
CCR2H
anyway.
To control multiple accesses to register
TICR
, an additional status bit
STARL
:TEC (TIC
Executing) is provided which signals that the transmission command of currently
programmed ’TIC’ is accepted but not yet completely executed. Further access to
register
TICR
is only allowed if bit
STARL
:TEC is ‘0’ again.
4.4.4.3
Out-of-band Flow Control
Transmitter:
The transmitter output is enabled if CTS signal is ‘LOW’ AND the XON state is reached
in case of in-band flow control is enabled. If the in-band flow control is disabled
(
CCR2H
:FLON = ‘0’), the transmitter is only controlled by the CTS signal.
Nevertheless setting bit
CCR1H
:FCTS = ‘1’ allows the transmitter to send data
independent of the condition of the CTS signal, the in-band flow control (XON/XOFF)
mechanism would still be operational if enabled via bit
CCR2H
:FLON = ‘1’.
Receiver:
For some applications it is desirable to provide means of out-of-band flow control to
indicate to the far end transmitter that the local receiver’s buffer is getting full.
This flow control can be used between two DTEs as shown in
Figure 47
and between a
DTE and a DCE (MODEM) as shown in
Figure 48
that supports this kind of bi-directional
flow control.
Setting bit
CCR1H
:FRTS = ‘1’ and
CCR1H
:RTS = ‘0’ invokes this out-of-band flow
control for the receiver. When the shadow part of the receive FIFO has reached a set
threshold of 28 bytes, the RTS signal is forced inactive (high). When the shadow part of
the receive FIFO is empty, the RTS is re-asserted (low). Note that the data is
immediately transferred from the shadow receive FIFO to the user accessible RFIFO (as
long as there is space available). So when the shadow receive FIFO reaches the 28
bytes threshold, there is 4 more byte storage available before overflow can occur. This
allows sufficient time for the far end transmitter to react to the change in the RTS signal
and stop sending more data.
Figure 47
shows the connection between two SCC devices as DTEs. The RTS of DTE-
A (SCC) feeds the CTS input of the second DTE-B (another SCC). For example while
Data Sheet
100
2000-09-14