peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 251

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

• If a transmit packet is distributed over more than one transmit buffer in memory, the
After transmission is complete, the optional generation of the ALLS interrupt indicates
that all transmit data has been sent on pin TxD.
Note: In HDLC Automode, the ’XF’ command may be replaced by the ’XIF’ command in
Figure 58
Data Sheet
Packet n:
Packet (n+1):
’XF’ command (without setting the ’XME’ bit) forces SEROCCO-M to request data
transfers from the external DMA controller from this buffer. A Transmit DMA Transfer
End (TDTE) interrupt is generated whenever a block of <XBC> bytes is completely
transferred. For the last buffer, containing the end of the transmit packet, the ’XF’
command is issued together with bit ’XME’ set (refer to
(write transmit byte count with command
the same register, when transmission of an I-frame is desired.
(prepare external DMA controller
(prepare external DMA controller
DMA Transmit (Single Buffer per Packet)
(write transmit byte count with
<XBC> transmit data
with buffer base address)
with buffer base address)
command bit 'XF'+'XME')
ALLS interrupt (optional)
DMA transfer of
CPU / MEMORY
TDTE interrupt
bit 'XF'+'XME')
bytes
251
...
...
SEROCCO-M
XBC
TFIFO
TFIFO
TFIFO
XBC
Figure
59).
Programming
PEB 20532
PEF 20532
2000-09-14