peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 116

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

5
5.1
The SEROCCO-M global registers are used to configure and control the Serial
Communication Controllers (SCCs), General Purpose Pins (GPP) and DMA operation.
All registers are 8-bit organized registers, but grouped and optimized for 16 bit access.
16 bit access is supported to even addresses only.
Table 15
Table 15
Offset Ch
Global registers:
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
Channel specific registers:
10
11
Data Sheet
A
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
60
61
B
H
H
provides an overview about all on-chip registers:
Register Description
Register Overview
GSTAR
GPISH
RFIFO
GPISL
DISR
read
Register Overview
Reserved
Reserved
GPDATH
Register
GPDATL
GPDIRH
GCMDR
GMODE
GPDIRL
DCMDR
GPIMH
GPIML
DIMR
XFIFO
write
Res
00
0B
00
07
FF
-
-
07
FF
00
00
00
00
77
-
-
Val
H
H
H
H
H
H
H
H
H
H
H
H
Global Command Register
Global Mode Register
Global Status Register
GPP Direction Register (Low Byte)
GPP Direction Register (High Byte)
GPP Data Register (Low Byte)
GPP Data Register (High Byte)
GPP Interrupt Mask Register (Low Byte)
GPP Interrupt Mask Register (High Byte)
GPP Interrupt Status Register (Low Byte) 132
GPP Interrupt Status Register (High Byte) 132
DMA Command Register
DMA Interrupt Status Register
DMA Interrupt Mask Register
Receive/Transmit FIFO (Low Byte)
Receive/Transmit FIFO (High Byte)
116
Meaning
Register Description
PEB 20532
PEF 20532
2000-09-14
121
122
124
126
126
128
128
130
130
135
137
138
138
134
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