peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 33

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

Table 2
Pin No.
Data Sheet
P-TQFP-
100-3
85
88
87
89
External DMA Interface
Symbol In (I)
DACKA I
DRTB
DRRB
DACKB
GP0
GP1
GP2
Out (O)
O
I/O
O
I/O
I
I/O
Function
DMA Acknowledge Channel A
A low signal on this pin informs the SEROCCO-M
that the requested DMA cycle controlled via
DRTA or DRRA of this channel is in progress, i.e.
the DMA controller has achieved bus mastership
from the CPU and will start data transfer cycles
(either write or read). In conjunction with a read or
write operation this input serves as Access
Enable (similar to CS) to the respective FIFOs. If
DACKA is active, the input to pins A(7:0) and CS
is ignored and the FIFOs are implicitly selected.
If not used, a pull-up resistor to V
this pin.
DMA Request Transmitter Channel B
(corresponding to channel A)
General Purpose Pin #0
If DMA support is not enabled, this pin serves as
a general pupose input/output pin.
After reset this pin serves as a general purpose
input. A pull-up resistor to V
DMA Request Receiver Channel B
(corresponding to channel A)
General Purpose Pin #1
If DMA support is not enabled, this pin serves as
a general pupose input/output pin.
After reset this pin serves as a general purpose
input. A pull-up resistor to V
DMA Acknowledge Channel B
(corresponding to channel A)
General Purpose Pin #2
If DMA support is not enabled, this pin serves as
a general pupose input/output pin.
A pull-up resistor to V
pin is not used.
33
DD3
is recommended if this
DD3
DD3
is recommended.
is recommended.
Pin Descriptions
DD
is required for
PEB 20532
PEF 20532
2000-09-14