peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 147

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

Data Sheet
For a write access to the register, the new value gets OR’ed with the current register
contents.
The ’CEC’ bit in register
STI
TRES
XIF
Start Timer Command
Self-clearing command bit:
HDLC Automode:
In HDLC Automode the timer is used internally for the autonomous
protocol support functions. The timer is started automatically by the SCC
when an I-Frame is sent out and needs to be acknowledged.
If the ’STI’ command is issued by software:
STI=’1’
All protocol modes except HDLC Automode:
In these modes the timer is operating as a general purpose timer.
STI=’1’
Timer Reset
Self-clearing command bit.
This bit deactivates timer operation:
TRES=’0’
TRES=’1’
Transmit I-Frame
Self-clearing command bit.
This command bit is significant in HDLC Automode only.
XIF=’1’
STARL/STARH
An S-Frame with poll bit set is sent out and the internal
timer is started expecting an acknowledge from the
remote station via an I- or S-Frame.
The timer is stopped after receiving an acknowledge
otherwise the timer expires generating a timer interrupt.
Note: In HDLC Automode, bit ’TMD’ in register
This commands starts timer operation.
The timer can be stopped by setting bit ’TRES’.
Note: Bit ’TMD’ in register
Timer operation enabled.
Timer operation stopped.
Initiates the transmission of an I-frame in auto-mode.
Additional to the opening flag, the address and control
fields of the frame are added by SEROCCO-M.
must be set to ’1’
proper operation
is the OR-function over all command bits.
5-147
Register Description (CMDRH)
TIMR3
must be cleared for
PEB 20532
PEF 20532
(hdlc mode)
(all modes)
(all modes)
2000-09-14
TIMR3