peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 225

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

Data Sheet
SUEX
BRK
BRKT
PLLA
CDSC
Signalling Unit Counter Exceeded Interrupt
This bit is set to ’1’, if 256 correct or incorrect SU’s have been received
and the internal counter is reset to 0.
Break Interrupt
This bit is set to ’1’, if a break condition was detected on the receive line,
i.e. a low level for a time equal to (character length + parity bit + stop
bit(s)) bits depending on the selected ASYNC character format.
Break Terminated Interrupt
This bit is set to ’1’, if a previously detected break condition on the
receive line is terminated by a low to high transition.
DPLL Asynchronous Interrupt
This bit is only valid, if the receive clock is derived from the internal DPLL
and FM0, FM1 or Manchester data encoding is selected (depending on
the selected clock mode and data encoding mode). It is set to ’1’ if the
DPLL
synchronization has been regained again. If the transmitter is supplied
with a clock derived from the DPLL, transmission is also interrupted.
Carrier Detect Status Change Interrupt
This bit is set to ’1’, if a state transition has been detected at signal CD.
Because only a state transition is indicated via this interrupt, the current
status can be evaluated by reading bit ’CD’ in status register STARH.
Note: A receive clock must be provided to detect a transition of CD.
has
lost
synchronization.
225
Reception
Register Description
is
disabled
(async mode)
(async mode)
PEB 20532
PEF 20532
(hdlc mode)
(all modes)
(all modes)
2000-09-14
until