peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 10

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

List of Figures
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Data Sheet
HDLC Receive Data Processing in Address Mode 0 . . . . . . . . . . . . . . 87
SCC Transmit Data Flow (HDLC Modes) . . . . . . . . . . . . . . . . . . . . . . 88
PPP Mapping/Unmapping Example. . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Asynchronous Character Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Out-of-Band DTE-DTE Bi-directional Flow Control . . . . . . . . . . . . . . 101
Out-of-Band DTE-DCE Bi-directional Flow Control . . . . . . . . . . . . . . 102
BISYNC Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Processing of Received Frames in Auto Mode . . . . . . . . . . . . . . . . . 107
Timer Procedure/Poll Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Transmission/Reception of I-Frames and Flow Control . . . . . . . . . . . 110
Flow Control: Reception of S-Commands and Protocol Errors . . . . . 110
No Data to Send: Data Reception/Transmission . . . . . . . . . . . . . . . . 113
Data Transmission (without error), Data Transmission (with error) . . 113
Interrupt Driven Data Transmission (Flow Diagram) . . . . . . . . . . . . . 247
Interrupt Driven Data Reception (Flow Diagram) . . . . . . . . . . . . . . . . 249
DMA Transmit (Single Buffer per Packet) . . . . . . . . . . . . . . . . . . . . . 251
Fragmented DMA Transmission (Multiple Buffers per Packet) . . . . . 252
DMA Receive (Single Buffer per Packet) . . . . . . . . . . . . . . . . . . . . . . 254
Fragmented Reception per DMA (Example) . . . . . . . . . . . . . . . . . . . 255
Fragmented Reception Sequence (Example) . . . . . . . . . . . . . . . . . . 256
Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 259
Microprocessor Interface Clock Timing . . . . . . . . . . . . . . . . . . . . . . . 261
Infineon/Intel Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Infineon/Intel Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Infineon/Intel DMA Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . 263
Infineon/Intel DMA Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . 263
Infineon/Intel Multiplexed Address Timing . . . . . . . . . . . . . . . . . . . . . 263
Motorola Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Motorola Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Motorola DMA Read Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Motorola DMA Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Receive Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Transmit Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Clock Mode 1 Strobe Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Clock Mode 4 Receive Gating Timing . . . . . . . . . . . . . . . . . . . . . . . . 273
Clock Mode 4 Transmit Gating Timing. . . . . . . . . . . . . . . . . . . . . . . . 273
Clock Mode 5 Frame Synchronisation Timing . . . . . . . . . . . . . . . . . . 274
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Block Diagram of Test Access Port and Boundary Scan Unit . . . . . . 277
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PEB 20532
PEF 20532
2000-09-14
Page