peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 149

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

Data Sheet
XME
XREP
RMC
RNR
RSUC
Transmit Message End
Self-clearing command bit:
XME=’1’
Transmission Repeat Command
Self-clearing command bit:
XREP=’1’
Receive Message Complete
Self-clearing command bit:
RMC=’1’
Receiver Not Ready Command
NON self-clearing command bit:
This command bit is significant in HDLC Automode only.
RNR=’0’
RNR=’1’
Reset Signaling Unit Counter
Self-clearing command bit:
This command bit is significant if HDLC SS7 mode is selected.
RSUC=’1’
Indicates that the data block written last to the XFIFO
contains the end of the packet. This bit should always be
set in conjunction with a transmit command (’XF’ or ’XIF’).
If bit ’XREP’ is set together with bit ’XME’ and ’XF’,
SEROCCO-M repeatedly transmits the contents of the
XFIFO (1..32 bytes).
The cyclic transmission can be stopped with the ’XRES’
command.
With this bit the CPU indicates to SEROCCO-M that the
current receive data has been fetched out of the RFIFO.
Thus the corresponding space in the RFIFO can be
released and re-used by SEROCCO-M for further
incoming data.
Forces the receiver to enter its ’receiver-ready’ state. The
receiver acknowledges received poll or I-Frames with a
’receiver-ready’ indication.
Forces the receiver to enter its ’receiver-not-ready’ state.
The receiver acknowledges received poll or I-Frames with
a ’receiver-not-ready’ indication.
The Signaling System #7 (SS7) unit counter is reset.
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Register Description (CMDRH)
(hdlc/bisync modes)
PEB 20532
PEF 20532
(hdlc mode)
(hdlc mode)
(hdlc mode)
(all modes)
2000-09-14