peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 82
peb20532
Manufacturer Part Number
peb20532
Description
2 Channel Serial Optimized Communication Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB20532.pdf
(282 pages)
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4
The following
desired protocol mode is selected via bit fields in the channel configuration registers
CCR0L, CCR0H,
Table 12
1)
All modes are discussed in details in this chapter.
Data Sheet
Register
(HDLC/SDLC/PPP protocol engine)
HDLC Automode
(LAP D / LAP B / SDLC-NRM)
HDLC Address Mode 2
HDLC Address Mode 1
HDLC Address Mode 0
Signaling System #7 (SS7) Operation
Bit Synchronous PPP Mode
Octet Synchronous PPP Mode
Asynchronous PPP Mode
Extended Transparent Mode
Register
(ASYNC protocol engine)
Asynchronous Mode
Isochronous Mode
Register
(BISYNC protocol engine)
Bisynchronous Mode
Monosynchronous Mode
Extended transparent mode is a fully bit-transparent transmission/reception mode which is treated as sub-
mode of the HDLC/SDLC/PPP block.
CCR0H
CCR0H
CCR0H
Detailed Protocol Description
Table 12
Protocol Mode Overview
CCR2L
- Bit Field SM(1:0) = ’00’ Register
- Bit Field SM(1:0) = ’11’ Register
- Bit Field SM(1:0) = ’10’ Register
provides an overview of all supported protocol modes and . The
and CCR3L.
1)
16 bit
8 bit
16 bit
8 bit
82
MDS
’00’
’00’
’01’
’01’
’10’
’10’
’10’
’10’
’11’
BCR
’1’
’0’
EBIM
’1’
’0’
CCR2L
CCR0L
CCR0L
Detailed Protocol Description
ADM
’1’
’0’
’1’
’0’
’1’
’0’
’0’
’0’
’1’
- Bit Field:
- Bit Field:
- Bit Field:
’00’
’00’
’11’
’01’
’10’
’00’
PPPM
PEB 20532
PEF 20532
2000-09-14
CCR3L
ESS7
’0’
’1’
’0’
’0’
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