peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 152

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

Data Sheet
VIS
PSD
BCR
Masked Interrupts Visible
VIS=’0’
VIS=’1’
Note: Interrupts masked in registers
DPLL Phase Shift Disable
This option is only applicable in the case of NRZ or NRZI line encoding
is selected.
PSD=’0’
PSD=’1’
Bit Clock Rate
This bit is only valid in asynchronous PPP and ASYNC protocol mode
and only in clock modes not using the DPLL (0, 1, 3b, 7b). It is also
invalid in clock mode 4.
BCR=’0’
BCR=’1’
interrupt.
Masked interrupt status bits are not displayed in the
interrupt status registers (ISR0..ISR2).
Masked interrupt status bits are visible and automatically
cleared after interrupt status register (ISR0..ISR2) read
access.
Normal DPLL operation.
The phase shift function of the DPLL is disabled. The
windows for phase adjustment are extended.
Selects isochronous operation with bit clock rate 1. Data
bits are sampled once.
Selects standard asynchronous operation with bit clock
rate 16. Using 16 samples per bit, data bits are sampled 3
times around the nominal bit center. The resulting bit
value is determined by majority decision of the 3 samples.
For correct operation NRZ data encoding has to be
selected.
5-152
IMR0..IMR2
Register Description (CCR0H)
(async PPP, ASYNC modes)
will not generate an
PEB 20532
PEF 20532
(all modes)
(all modes)
2000-09-14