peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 41
peb20532
Manufacturer Part Number
peb20532
Description
2 Channel Serial Optimized Communication Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB20532.pdf
(282 pages)
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The functional blocks of SEROCCO-M can be divided into two major domains:
– the microprocessor interface of SEROCCO-M provides access to on-chip registers
– the Serial Communication Controller (SCC) is capable of processing bit-synchronous
Data exchange between the serial communication controller and the microprocessor
interface is performed using FIFOs, decoupling these two domains.
3.1
Figure 8
Data Sheet
and to the "user" portion of the receive and transmit FIFOs (RFIFO/XFIFO). Optionally
these FIFOs can be accessed by an external 4-channel DMA controller.
(HDLC/SDLC/bitsync PPP) and octet-synchronous (octet-sync PPP) as well as fully
transparent data traffic.
26
6
Functional Overview
Block Diagram
External DMA
Block Diagram
Interface
Transmit FIFO
Transmit FIFO
Receive FIFO
Receive FIFO
(32 Byte)
(32 Byte)
(32 Byte)
(32 Byte)
JTAG Test
Interface
5
Serial Channel A
Serial Channel B
Transmit FIFO
Receive FIFO
(32 Byte)
(32 Byte)
41
LAP Control
Transmit
Machine
Machine
Protocol
Protocol
Receive
TSA
Functional Overview
Decoder/
Collision
Detection
DPLL
Clock
Control
Oscillator
BRG
PEB 20532
PEF 20532
2000-09-14
7
7
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